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| ADVANCED AND EVER ADVANCING MITSUBISHI ELECTRIC MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES 3800 Group User's Manual MITSUBISHI ELECTRIC Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Preface This user's manual describes Mitsubishi's CMOS 8bit microcomputers 3800 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 3800 Group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. For details of software, refer to the "SERIES MELPS 740 BEFORE USING THIS USER'S MANUAL This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems development. Be sure to refer to this chapter. 1. Organization q CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. q CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, electric characteristics, a list of registers, the masking confirmation (mask ROM version), and mark specifications which are to be submitted when ordering. 2. Structure of register The figure of each register structure describes its functions, contents at reset, and attributes as follows : (Note 2) Bits b7 b6 b5 b4 b3 b2 b1 b0 0 Bit attributes (Note 1) Contents immediately after reset release CPU mode register (CPUM) [Address : 3B16] B 0 1 2 3 4 5 6 7 Stack page selection bit Name Processor mode bits b1 b0 Function 0 0 : Single-chip mode 01: 1 0 : Not available 11: 0 : 0 page 1 : 1 page At reset RW 0 0 0 0 0 1 T T Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0." Fix this bit to "0." Main clock (XIN-XOUT) stop bit Internal system clock selection bit 0 : Operating 1 : Stopped 0 : XIN-XOUT selected 1 : XCIN-XCOUT selected ! ! : Bit in which nothing is arranged : Bit that is not used for control of the corresponding function Note 1. Contents immediately after reset release 0******"0" at reset release 1******"1" at reset release Undefined******Undefined or reset release T ******Contents determined by option at reset release Note 2. Bit attributes******The attributes of control register bits are classified into 3 bytes : read-only, write-only and read and write. In the figure, these attributes are represented as follows : R******Read ******Read enabled !******Read disabled W******Write ******Write enabled ! ******Write disabled LIST OF GROUPS HAVING THE SIMILAR FUNCTIONS 3800 group, one of the CMOS 8-bit microcomputer 38000 series presented in this user's manual is provided with standard functions. The basic functions of the 3800, 3802, 3806 and 3807 groups having the same functions are shown below. For the detailed functions of each group, refer to the related data book and user's manual. List of groups having the same functions Group Function Pin (Package type) 3800 group 64 pin * 64P4B * 64P6N-A * 64P6D-A As of September 1995 3806 group 80 pin * 80P6N-A * 80P6S-A * 80P6D-A 3802 group 64 pin * 64P4B * 64P6N-A 3807 group 80 pin * 80P6N-A Clock generating circuit 1 circuit 1 circuit 1 circuit 2 circuit <8-bit> Timer <8-bit> Prescaler : 3 Timer : 4 <8-bit> Prescaler : 3 Timer : 4 <8-bit> Prescaler : 3 Timer : 4 Timer : 3 <16-bit> Timer X/Y : 2 Timer A/B : 2 UART or Clock synchronous ! 1 Clock synchronous ! 1 8-bit ! 13-channel UART or Clock synchronous ! 1 UART or Clock synchronous ! 1 Clock synchronous ! 1 8-bit ! 8-channel UART or Clock synchronous ! 1 Clock synchronous ! 1 8-bit ! 8-channel Serial I/O -- A-D converter D-A converter Mask ROM Memory type One Time PROM EPROM RAM -- -- 8K 16K 24K 32K (Note 1) (Note 1) V 8K (Note 1) 8-bit ! 2-channel 16K (Note 1) 8-bit ! 2-channel 8-bit ! 4-channel 16K 16K 16K 512 Real time port output Analog comparator Watchdog timer (Note 1) 24K (Note 1) 32K 12K 16K 24K 32K 48K (Note 1) (Note 1) (Note 3) (Note 3) (Note 3) 16K 8K (Note 1) -- 32K -- -- -- -- -- 384 -- -- 32K (Note 1) -- -- -- (Note 2) 24K -- 48K (Note 3) -- 16K -- 32K -- 32K -- 24K -- 48K (Note 2) 384 384 512 640 384 384 640 1024 384 384 512 1024 1024 PWM output Remarks Notes 1: 2: 3: V. Extended operating temperature version available High-speed version available Extended operating temperature version and High-speed version available ROM expansion Table of contents Table of contents CHAPTER 1. HARDWARE DESCRIPTION ................................................................................................................................ 1-2 FEATURES ...................................................................................................................................... 1-2 APPLICATIONS .............................................................................................................................. 1-2 PIN CONFIGURATION .................................................................................................................. 1-2 FUNCTIONAL BLOCK ................................................................................................................... 1-4 PIN DESCRIPTION ........................................................................................................................ 1-5 PART NUMBERING ....................................................................................................................... 1-6 GROUP EXPANSION .................................................................................................................... 1-7 GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) ................... 1-9 FUNCTIONAL DESCRIPTION .................................................................................................... 1-10 Central Processing Unit (CPU) ............................................................................................ 1-10 Memory .................................................................................................................................... 1-14 I/O Ports .................................................................................................................................. 1-16 Interrupts ................................................................................................................................. 1-18 Timers ...................................................................................................................................... 1-20 Serial I/O ................................................................................................................................. 1-22 Reset Circuit ........................................................................................................................... 1-26 Clock Generating Circuit ....................................................................................................... 1-28 Processor Modes .................................................................................................................... 1-29 NOTES ON PROGRAMMING ..................................................................................................... 1-31 Processor Status Register .................................................................................................... 1-31 Interrupts ................................................................................................................................. 1-31 Decimal Calculations.............................................................................................................. 1-31 Timers ...................................................................................................................................... 1-31 Multiplication and Division Instructions ............................................................................... 1-31 Ports ......................................................................................................................................... 1-31 Serial I/O ................................................................................................................................. 1-31 Instruction Execution Time .................................................................................................... 1-31 Memory Expansion Mode and Microprocessor Mode ....................................................... 1-31 DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-32 ROM PROGRAMMING METHOD .............................................................................................. 1-32 FUNCTIONAL DESCRIPTION SUPPLEMENT ......................................................................... 1-33 Interrupt ................................................................................................................................... 1-33 Timing After Interrupt ............................................................................................................. 1-34 3800 GROUP USER'S MANUAL i Table of contents CHAPTER 2. APPLICATION 2.1 I/O port ..................................................................................................................................... 2.1.1 Memory map of I/O port ............................................................................................... 2.1.2 Related registers ............................................................................................................ 2.1.3 Handling of unused pins ............................................................................................... 2-2 2-2 2-3 2-4 2.2 Timer ......................................................................................................................................... 2-5 2.2.1 Memory map of timer .................................................................................................... 2-5 2.2.2 Related registers ............................................................................................................ 2-6 2.2.3 Timer application examples ........................................................................................ 2-11 2.3 Serial I/O ................................................................................................................................ 2-23 2.3.1 Memory map of serial I/O ........................................................................................... 2-23 2.3.2 Related registers .......................................................................................................... 2-24 2.3.3 Serial I/O connection examples ................................................................................. 2-28 2.3.4 Setting of serial I/O transfer data format ................................................................. 2-30 2.3.5 Serial I/O application examples ................................................................................. 2-31 2.4 Processor mode ................................................................................................................... 2-49 2.4.1 Memory map of processor mode ............................................................................... 2-49 2.4.2 Related register ............................................................................................................ 2-49 2.4.3 Processor mode application examples ...................................................................... 2-50 2.5 Reset ....................................................................................................................................... 2-54 2.5.1 Connection example of reset IC ................................................................................ 2-54 CHAPTER 3. APPENDIX 3.1 Electrical characteristics ..................................................................................................... 3-2 3.1.1 Absolute maximum ratings ............................................................................................ 3-2 3.1.2 Recommended operating conditions ............................................................................ 3-2 3.1.3 Electrical characteristics ................................................................................................ 3-3 3.1.4 Timing requirements and Switching characteristics .................................................. 3-4 3.1.5 Absolute maximum ratings (Extended operating temperature version) .................. 3-8 3.1.6 Recommended operating conditions(Extended operating temperature version) .... 3-8 3.1.7 Electrical characteristics (Extended operating temperature version) ...................... 3-9 3.1.8 Timing requirements and Switching characteristics (Extended operating temperature version).......................................................... 3-10 3.1.9 Timing diagram ............................................................................................................. 3-12 3.2 Standard characteristics .................................................................................................... 3-15 3.2.1 Power source current characteristic examples ........................................................ 3-15 3.2.2 Port standard characteristic examples ...................................................................... 3-16 3.3 Notes on use ........................................................................................................................ 3-18 3.3.1 Notes on interrupts ...................................................................................................... 3-18 3.3.2 Notes on the serial I/O ............................................................................................... 3-18 3.3.3 Notes on the RESET pin ............................................................................................ 3-19 3.3.4 Notes on input and output pins ................................................................................. 3-20 ii 3800 GROUP USER'S MANUAL Table of contents 3.3.5 Notes on memory expansion mode and microprocessor mode ............................ 3-21 3.3.6 Notes on built-in PROM .............................................................................................. 3-22 3.4 Countermeasures against noise ...................................................................................... 3-24 3.4.1 Shortest wiring length .................................................................................................. 3-24 3.4.2 Connection of a bypass capacitor across the Vss line and the Vcc line ............ 3-25 3.4.3 Consideration for oscillator ......................................................................................... 3-26 3.4.4 Setup for I/O ports ....................................................................................................... 3-26 3.4.5 Providing of watchdog timer function by software .................................................. 3-27 3.5 List of registers ................................................................................................................... 3-28 3.6 Mask ROM ordering method ............................................................................................. 3-37 3.7 Mark specification form ..................................................................................................... 3-51 3.8 Package outline.................................................................................................................... 3-53 3.9 Machine Instructions .......................................................................................................... 3-56 3.10 List of instruction codes ................................................................................................. 3-66 3.11 SFR memory map .............................................................................................................. 3-67 3.12 Pin configuration ............................................................................................................... 3-68 3800 GROUP USER'S MANUAL iii List of figures List of figures CHAPTER 1 HARDWARE Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 Pin configuration of M38002M4-XXXFP/M38003M6-XXXHP ....................................... 1-2 2 Pin configuration of M38002M4-XXXSP ......................................................................... 1-3 3 Functional block diagram .................................................................................................. 1-4 4 Part numbering ................................................................................................................... 1-6 5 Memory expansion plan .................................................................................................... 1-7 6 Memory expansion plan (Extended operating temperature version) .......................... 1-9 7 740 Family CPU register structure ................................................................................ 1-10 8 Register push and pop at interrupt generation and subroutine call ........................ 1-11 9 Structure of CPU mode register .................................................................................... 1-13 10 Memory map diagram .................................................................................................... 1-14 11 Memory map of special function register (SFR) ....................................................... 1-15 12 Port block diagram (single-chip mode) ....................................................................... 1-17 13 Interrupt control .............................................................................................................. 1-19 14 Structure of interrupt-related registers ........................................................................ 1-19 15 Structure of timer XY register ...................................................................................... 1-20 16 Block diagram of timer X, timer Y, timer 1, and timer 2 ........................................ 1-21 17 Block diagram of clock synchronous serial I/O ......................................................... 1-22 18 Operation of clock synchronous serial I/O function .................................................. 1-22 19 Block diagram of UART serial I/O............................................................................... 1-23 20 Operation of UART serial I/O function ....................................................................... 1-24 21 Structure of serial I/O control registers ...................................................................... 1-25 22 Example of reset circuit ................................................................................................ 1-26 23 Internal status of microcomputer after reset .............................................................. 1-26 24 Timing of reset ............................................................................................................... 1-27 25 Ceramic resonator circuit .............................................................................................. 1-28 26 External clock input circuit ........................................................................................... 1-28 27 Block diagram of clock generating circuit .................................................................................. 1-28 28 Memory maps in various processor modes ............................................................... 1-29 29 Structure of CPU mode register .................................................................................. 1-29 30 ONW function timing ...................................................................................................... 1-30 31 Programming and testing of One Time PROM version ........................................... 1-32 32 Timing chart after an interrupt occurs ........................................................................ 1-34 33 Time up to execution of the interrupt processing routine ....................................... 1-34 CHAPTER 2 APPLICATION Fig. 2.1.1 Memory map of I/O port related registers ............................................................... 2-2 Fig. 2.1.2 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6, 7) .......................................................... 2-3 Fig. 2.1.3 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6, 7) ........................... 2-3 Fig. Fig. Fig. Fig. Fig. Fig. 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 Memory map of timer related registers ..................................................................... 2-5 Structure of Prescaler 12, Prescaler X, Prescaler Y .............................................. 2-6 Structure of Timer 1 .................................................................................................... 2-6 Structure of Timer 2, Timer X, Timer Y................................................................... 2-7 Structure of Timer XY mode register ....................................................................... 2-8 Structure of Interrupt request register 1 .................................................................. 2-9 3800 GROUP USER'S MANUAL i List of figures Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.2.7 Structure of Interrupt request register 2 ................................................................... 2-9 2.2.8 Structure of Interrupt control register 1 .................................................................. 2-10 2.2.9 Structure of Interrupt control register 2 .................................................................. 2-10 2.2.10 Connection of timers and setting of division ratios [Clock function] ................ 2-12 2.2.11 Setting of related registers [Clock function] ......................................................... 2-13 2.2.12 Control procedure [Clock function] ........................................................................ 2-14 2.2.13 Example of a peripheral circuit .............................................................................. 2-15 2.2.14 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output] .......... 2-15 2.2.15 Setting of related registers [Piezoelectric buzzer output]................................... 2-16 2.2.16 Control procedure [Piezoelectric buzzer output] .................................................. 2-16 2.2.17 A method for judging if input pulse exists ........................................................... 2-17 2.2.18 Setting of related registers [Measurement of frequency] ................................... 2-18 2.2.19 Control procedure [Measurement of frequency]................................................... 2-19 2.2.20 Connection of the timer and setting of the division ratio [Measurement of pulse width] ........... 2-20 2.2.21 Setting of related registers [Measurement of pulse width] ................................ 2-21 2.2.22 Control procedure [Measurement of pulse width] ................................................ 2-22 2.3.1 Memory map of serial I/O related registers ........................................................... 2-23 2.3.2 Structure of Transmit/Receive buffer register ........................................................ 2-24 2.3.3 Structure of Serial I/O status register .................................................................... 2-24 2.3.4 Structure of Serial I/O control register ................................................................... 2-25 2.3.5 Structure of UART control register ......................................................................... 2-25 2.3.6 Structure of Baud rate generator ............................................................................ 2-26 2.3.7 Structure of Interrupt edge selection register ....................................................... 2-26 2.3.8 Structure of Interrupt request register 1 ................................................................ 2-27 2.3.9 Structure of Interrupt control register 1 ................................................................. 2-27 2.3.10 Serial I/O connection examples (1) ...................................................................... 2-28 2.3.11 Serial I/O connection examples (2) ...................................................................... 2-29 2.3.12 Setting of Serial I/O transfer data format ............................................................ 2-30 2.3.13 Connection diagram [Communication using a clock synchronous serial I/O] 2-31 2.3.14 Timing chart [Communication using a clock synchronous serial I/O] ............. 2-31 2.3.15 Setting of related registers at a transmitting side [Communication using a clock synchronous serial I/O] .................................. 2-32 2.3.16 Setting of related registers at a receiving side [Communication using a clock synchronous serial I/O] .................................. 2-33 2.3.17 Control procedure at a transmitting side [Communication using a clock synchronous serial I/O] .................................. 2-34 2.3.18 Control procedure at a receiving side[Communication using a clock synchronous serial I/O] . 2-35 2.3.19 Connection diagram [Output of serial data] ......................................................... 2-36 2.3.20 Timing chart [Output of serial data] ...................................................................... 2-36 2.3.21 Setting of serial I/O related registers [Output of serial data] ............................ 2-37 2.3.22 Setting of serial I/O transmission data [Output of serial data].......................... 2-37 2.3.23 Control procedure of serial I/O [Output of serial data] ...................................... 2-38 2.3.24 Connection diagram [Cyclic transmission or reception of block data between microcomputers] 2-39 2.3.25 Timing chart [Cyclic transmission or reception of block data between microcomputers] ........ 2-40 2.3.26 Setting of related registers [Cyclic transmission or reception of block data between microcomputers] . 2-40 2.3.27 Control in the master unit ....................................................................................... 2-41 2.3.28 Control in the slave unit ......................................................................................... 2-42 2.3.29 Connection diagram [Communication using UART] ............................................ 2-43 2.3.30 Timing chart [Communication using UART] ......................................................... 2-43 ii 3800 GROUP USER'S MANUAL List of figures Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.3.31 2.3.32 2.3.33 2.3.34 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 Setting of related registers at a transmitting side [Communication using UART] ........................ 2-45 Setting of related registers at a receiving side [Communication using UART] ............................ 2-46 Control procedure at a transmitting side [Communication using UART] ......... 2-47 Control procedure at a receiving side [Communication using UART] .............. 2-48 Memory map of processor mode related register ................................................ 2-49 Structure of CPU mode register .............................................................................. 2-49 Expansion example of ROM and RAM .................................................................. 2-50 Read-cycle (OE access, SRAM).............................................................................. 2-51 Read-cycle (OE access, EPROM) ........................................................................... 2-51 Write-cycle (W control, SRAM) ................................................................................ 2-52 Application example of the ONW function ............................................................. 2-53 Fig. 2.5.1 Example of Poweron reset circuit ........................................................................... 2-54 Fig. 2.5.2 RAM back-up system ................................................................................................ 2-54 3800 GROUP USER'S MANUAL iii List of figures CHAPTER 3 APPENDIX Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.1.1 3.1.2 3.1.3 3.1.4 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 Circuit Timing Timing Timing for measuring output switching characteristics ......................................... 3-11 diagram (in single-chip mode) .................................................................... 3-12 diagram (in memory expansion mode and microprocessor mode) (1) 3-13 diagram (in memory expansion mode and microprocessor mode) (2) 3-14 Power source current characteristic example ....................................................... 3-15 Power source current characteristic example (in wait mode) ............................. 3-15 Standard characteristic example of CMOS output port at P-channel drive(1) . 3-16 Standard characteristic example of CMOS output port at P-channel drive(2) . 3-16 Standard characteristic example of CMOS output port at N-channel drive(1) 3-17 Standard characteristic example of CMOS output port at N-channel drive(2) 3-17 Fig. 3.3.1 Structure of interrupt control register 2 .................................................................. 3-18 Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 Wiring for the RESET pin ........................................................................................ 3-24 Wiring for clock I/O pins ........................................................................................... 3-25 Wiring for the VPP pin of the One Time PROM and the EPROM version ....... 3-25 Bypass capacitor across the VSS line and the VCC line ..................................... 3-25 Wiring for a large current signal line ..................................................................... 3-26 Wiring to a signal line where potential levels change frequently ...................... 3-26 Stepup for I/O ports .................................................................................................. 3-26 Watchdog timer by software .................................................................................... 3-27 3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6, 7) ........................................................ 3-28 3.5.2 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6, 7) ......................... 3-28 3.5.3 Structure of Transmit/Receive buffer register ....................................................... 3-29 3.5.4 Structure of Serial I/O status register .................................................................... 3-29 3.5.5 Structure of Serial I/O control register ................................................................... 3-30 3.5.6 Structure of UART control register ......................................................................... 3-30 3.5.7 Structure of Baud rate generator ............................................................................ 3-31 3.5.8 Structure of Prescaler 12, Prescaler X, Prescaler Y ........................................... 3-31 3.5.9 Structure of Timer 1 .................................................................................................. 3-32 3.5.10 Structure of Timer 2, Timer X, Timer Y .............................................................. 3-32 3.5.11 Structure of Timer XY mode register ................................................................... 3-33 3.5.12 Structure of Interrupt edge selection register ..................................................... 3-34 3.5.13 Structure of CPU mode register ............................................................................ 3-34 3.5.14 Structure of Interrupt request register 1 .............................................................. 3-35 3.5.15 Structure of Interrupt request register 2 .............................................................. 3-35 3.5.16 Structure of Interrupt control register 1 ............................................................... 3-36 3.5.17 Structure of Interrupt control register 2 ............................................................... 3-36 iv 3800 GROUP USER'S MANUAL List of tables List of tables CHAPTER 1 HARDWARE Table Table Table Table Table Table Table Table Table Table 1 Pin description ................................................................................................................. 1-5 2 List of supported products ............................................................................................. 1-8 3 List of supported products (Extended operating temperature version) .................. 1-9 4 Push and pop instructions of accumulator or processor status register .............. 1-11 5 Set and clear instructions of each bit of processor status register...................... 1-12 6 List of I/O port functions .............................................................................................. 1-16 7 Interrupt vector addresses and priority ...................................................................... 1-18 8 Functions of ports in memory expansion mode and microprocessor mode ........ 1-29 9 Programming adapter ................................................................................................... 1-32 10 Interrupt sources, vector addresses and interrupt priority.................................... 1-33 CHAPTER 2 APPLICATION Table 2.1.1 Handling of unused pins (in single-chip mode) ................................................... 2-4 Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode) ....... 2-4 Table 2.2.1 Function of CNTR0/CNTR1 edge switch bit .......................................................... 2-8 Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values .................... 2-44 CHAPTER 3 APPENDIX Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 3.1.1 Absolute maximum ratings ...................................................................................... 3-2 3.1.2 Recommended operating conditions ...................................................................... 3-2 3.1.3 Electrical characteristics .......................................................................................... 3-3 3.1.4 Timing requirements (1) .......................................................................................... 3-4 3.1.5 Timing requirements (2) .......................................................................................... 3-4 3.1.6 Switching characteristics (1) ................................................................................... 3-5 3.1.7 Switching characteristics (2) ................................................................................... 3-5 3.1.8 Timing requirements in memory expansion mode and microprocessor mode (1) ...................... 3-6 3.1.9 Switching characteristics in memory expansion mode and microprocessor mode (1) ............... 3-6 3.1.10 Timing requirements in memory expansion mode and microprocessor mode (2) .................... 3-7 3.1.11 Switching characteristics in memory expansion mode and microprocessor mode (2) ............ 3-7 3.1.12 Absolute maximum ratings (Extended operating temperature version) .......... 3-8 3.1.13 Recommended operating conditions (Extended operating temperature version) ...... 3-8 3.1.14 Electrical characteristics (Extended operating temperature version) .............. 3-9 3.1.15 Timing requirements (Extended operating temperature version) .................. 3-10 3.1.16 Switching characteristics (Extended operating temperature version) ............ 3-10 3.1.17 Timing requirements in memory expansion mode and microprocessor mode (Extended operating temperature version) ................................................... 3-11 Table 3.1.18 Switching characteristics in memory expansion mode and microprocessor mode (Extended operating temperature version) ................................................... 3-11 3800 GROUP USER'S MANUAL i List of tables Table 3.3.1 Programming adapter ............................................................................................. 3-22 Table 3.3.2 Setting of programming adapter switch ............................................................... 3-22 Table 3.3.3 Setting of PROM programmer address ................................................................ 3-23 Table 3.5.1 Function of CNTR0/CNTR1 edge switch bit ........................................................ 3-33 ii 3800 GROUP USER'S MANUAL CHAPTER 1 HARDWARE DESCRIPTION FEATURES APPLICATIONS PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD FUNCTIONAL DESCRIPTION SUPPLEMENT HARDWARE DESCRIPTION/FEATURES/APPLICATIONS/PIN CONFIGURATION DESCRIPTION The 3800 group is the 8-bit microcomputer based on the 740 family core technology. The 3800 group is designed for office automation equipment, household appliances and include four timers, serial I/O function. The various microcomputers in the 3800 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3800 group, refer to the section on group expansion. * Power source voltage ..................................................3.0 to 5.5 V * * * (Extended operating temperature version : 4.0 to 5.5 V) Power dissipation ............................................................... 32 mW Memory expansion possible Operating temperature range .................................... -20 to 85C (Extended operating temperature version : -40 to 85C) APPLICATIONS Office automation, factory automation, household appliances, and other consumer applications, etc. FEATURES * Basic machine-language instructions ....................................... 71 * The minimum instruction execution time ............................ 0.5 s (at 8 MHz oscillation frequency) * Memory size * * * * * ROM .................................................................. 8 K to 32 K bytes RAM ................................................................. 384 to 1024 bytes Programmable input/output ports ............................................. 58 Interrupts .................................................. 15 sources, 15 vectors Timers ............................................................................. 8 bit ! 4 Serial I/O ....................... 8-bit ! 1 (UART or Clock-synchronized) Clock generating circuit ....................... Internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) PIN CONFIGURATION (TOP VIEW) P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P37/RD P36/WR P35/SYNC P34/ P33/RESETOUT P32/ONW P31 P30 VCC P71 P70 P67 P66 P65 P64 P63 M38002M4-XXXFP M38003M6-XXXHP P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 VSS XOUT XIN P40 P41 RESET CNVSS P42/INT0 Package type : 64P6N-A/64P6D-A 64-pin plastic-molded QFP Fig. 1 Pin configuration of M38002M4-XXXFP/M38003M6-XXXHP 1-2 P62 P61 P60 P57 P56 P55/CNTR1 P54/CNTR0 P53/INT5 P52/INT4 P51/INT3 P50/INT2 P47/SRDY P46/SCLK P45/TXD P44/RXD P43/INT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3800 GROUP USER'S MANUAL HARDWARE PIN CONFIGURATION PIN CONFIGURATION (TOP VIEW) VCC P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55/CNTR1 P54/CNTR0 P53/INT5 P52/INT4 P51/INT3 P50/INT2 P47/SRDY P46/SCLK P45/TXD P44/RXD P43/INT1 P42/INT0 CNVSS RESET P41 P40 XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30 P31 P32/ONW P33/RESETOUT P34/ P35/SYNC P36/WR P37/RD P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15 P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 Package type : 64P4B 64-pin shrink plastic-molded DIP Fig. 2 Pin configuration of M38002M4-XXXSP 3800 GROUP USER'S MANUAL M38002M4-XXXSP 1-3 1-4 Reset input VSS RESET 27 26 32 1 FUNCTIONAL BLOCK DIAGRAM (Package : 64P4B) Clock input XIN VCC CNVSS Clock output XOUT 30 31 HARDWARE FUNCTIONAL BLOCK FUNCTIONAL BLOCK Fig. 3 Functional block diagram Data bus CPU Clock generating circuit RAM ROM X Prescaler 12 (8) Y S PC H PS CNTR0 CNTR1 PCL Prescaler Y (8) Prescaler X (8) A Timer 1 (8) Timer 2 (8) Timer X (8) 3800 GROUP USER'S MANUAL Serial I/O(8) INT2 to INT5 INT0, INT1 Timer Y (8) P7(2) P6(8) P5(8) P4(8) P3(8) P2(8) P1(8) P0(8) 23 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 28 29 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 I/O port P7 I/O port P6 I/O port P5 I/O port P4 I/O port P3 I/O port P2 I/O port P1 I/O port P0 HARDWARE PIN DESCRIPTION PIN DESCRIPTION Table 1. Pin description Pin VCC VSS CNVSS CNVSS * This pin controls the operation mode of the chip. * Normally connected to VSS. * If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed. * Reset input pin for active "L" * Input and output signals for the internal clock generating circuit. * Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. * If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * The clock is used as the oscillating source of system clock. * * * * * * 8 bit CMOS I/O port I/O direction register allows each pin to be individually programmed as either input or output. At reset this port is set to input mode. In modes other than single-chip, these pins are used as address, data, and control bus I/O pins. CMOS compatible input level CMOS 3-state output structure Name Power source Function Function except a port function * Apply voltage of 3.0 V to 5.5 V to VCC, and 0 V to VSS. (Extended operating temperature version : 4.0 V to 5.5 V) RESET XIN XOUT P00 - P07 P10 - P17 P20 - P27 P30 - P37 P40, P41 P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK, P47/SRDY P50/INT2 - P53/INT5 P54/CNTR0, P55/CNTR1 P56, P57 P60 - P67 Reset input Clock input Clock output I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 * 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure * External interrupt input pins * Serial I/O I/O pins I/O port P5 * 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure * External interrupt input pins * Timer X and Timer Y I/O pins I/O port P6 * 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure * 2-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure P70, P71 I/O port P7 3800 GROUP USER'S MANUAL 1-5 HARDWARE PART NUMBERING PART NUMBERING Product M3800 2 M 4 - XXX SP Package type SP : 64P4B package FP : 64P6N-A package HP : 64P6D-A package SS : 64S1B package FS : 64D0 package ROM number Omitted in some types. Normally, using hyphen When electrical characteristic, or division of quality identification code using alphanumeric character - : standard D : Extended operating temperature version ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version S : External ROM RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes Fig. 4 Part numbering 1-6 3800 GROUP USER'S MANUAL HARDWARE GROUP EXPANSION GROUP EXPANSION Mitsubishi plans to expand the 3800 group as follows: (1) S u p p o r t fo r m a s k R O M , O n e T i m e P R O M , E P RO M , and external ROM versions ROM/PROM capacity ................................... 8 K to 32 K bytes RAM capacity .............................................. 384 to 1024 bytes (2) Packages 64P4B ............................................ Shrink plastic molded DIP 64P6N-A ............................. 0.8 mm pitch plastic molded QFP 64P6D-A ............................. 0.5 mm pitch plastic molded QFP 64S1B ......................... Shrink ceramic DIP (EPROM version) 64D0 ................ 0.8 mm pitch ceramic LCC (EPROM version) Memory Expansion Plan ROM size (bytes) Mass product External ROM M38002S Mass product Being planned M38007M8/E8 32K M38004M8/E8 28K Mass product 24K M38003M6 20K Mass product 16K M38002M4/E4 12K Mass product 8K M38002M2/E2 192 256 384 512 RAM size (bytes) 640 768 896 1024 Note : Products under development or planning: the development schedule and specifications may be revised without notice. Fig. 5 Memory expansion plan 3800 GROUP USER'S MANUAL 1-7 HARDWARE GROUP EXPANSION Currently supported products are listed below. Table 2. List of supported products Product M38002M2-XXXSP M38002E2-XXXSP M38002E2SP M38002M2-XXXFP M38002E2-XXXFP M38002E2FP M38002M4-XXXSP M38002E4-XXXSP M38002E4SP M38002E4SS M38002M4-XXXFP M38002E4-XXXFP M38002E4FP M38002E4FS M38003M6-XXXSP M38003M6-XXXFP M38003M6-XXXHP M38004M8-XXXSP M38004E8-XXXSP M38004E8SP M38004E8SS M38004M8-XXXFP M38004E8-XXXFP M38004E8FP M38004E8FS M38002SSP M38002SFP (P) ROM size (bytes) ROM size for User in ( ) RAM size (bytes) Package As of September 1995 Remarks Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version External ROM type External ROM type 64P4B 8192 (8062) 384 64P6N-A 64P4B 16384 (16254) 64S1B-E 64P6N-A 64D0 64P4B 512 64P6N-A 64P6D-A 64P4B 32768 (32638) 64S1B-E 64P6N-A 64D0 64P4B 64P6N-A 384 24576 (24446) 640 0 384 1-8 3800 GROUP USER'S MANUAL HARDWARE GROUP EXPANSION GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) Mitsubishi plans to expand the 3800 group (extended operating temperature version) as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions ROM/PROM capacity ................................... 8 K to 32 K bytes RAM capacity ................................................ 384 to 640 bytes (2) Packages 64P4B ............................................ Shrink Plastic molded DIP 64P6N-A ............................. 0.8 mm pitch plastic molded QFP Memory Expansion Plan (Extended operating temperature version) ROM size (bytes) 32K Mass product M38004M8D 28K 24K 20K Mass product 16K M38002M4D/E4D 12K Mass product 8K M38002M2D 4K 192 256 384 512 RAM size (bytes) 640 768 896 1024 Fig. 6 Memory expansion plan (Extended operating temperature version) Currently supported products are listed below. Table 3. List of supported products (Extended operating temperature version) Product name M38002M2DXXXSP M38002M2DXXXFP M38002M4DXXXSP M38002E4DXXXSP M38002E4DSP M38002M4DXXXFP M38002E4DXXXFP M38002E4DFP M38004M8DXXXSP M38004M8DXXXFP (P) ROM size (bytes) ROM size for User in ( ) 8192 (8062) RAM size (bytes) 384 Package 64P4B 64P6N-A 64P4B 16384 (16254) 384 64P6N-A 32768 (32638) 64P4B 64P6N-A As of September 1995 Remarks Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version Mask ROM version 1024 3800 GROUP USER'S MANUAL 1-9 HARDWARE FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 3800 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 Stack pointer (S) The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is "0", then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is "1", then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are shown in Fig. 8. Accumulator (A) The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. Index register X (X), Index register Y (Y) Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to "1", the value contained in index register X becomes the address for the second OPERAND. Program counter (PC) The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL b0 Accumulator b0 Index Register X b0 Index Register Y b0 Stack Pointer b0 Program Counter b0 Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag NVTBDI ZC Fig. 7 740 Family CPU register structure 1-10 3800 GROUP USER'S MANUAL HARDWARE FUNCTIONAL DESCRIPTION On-going Routine Interrupt Request (Note 1) M(S) (PCH) Execute JSR (S) (S - 1) M(S) (PCH) (S) (S - 1) M(S) (PCL) (S) (S - 1) Subroutine M(S) (PCL) (S) (S - 1) M(S) (PS) (S) (S - 1) Interrupt Service Routine Store Return Address on Stack (Note 2) Store Return Address on Stack (Note 2) Store Contents of Processor Status Register on Stack Execute RTS (S) (S + 1) (PCL) M(S) (S) (S + 1) (PCH) M(S) Execute RTI (S) (S + 1) (PS) M(S) (S) (S + 1) (PCL) M(S) (S) (S + 1) (PCH) M(S) I Flag "0" to "1" Fetch the Jump Vector Restore Return Address Restore Contents of Processor Status Register Restore Return Address Notes 1 : The condition to enable the interrup t Interrupt enable bit is "1" Interrupt disable flag is "0" 2 : When an interrupt occurs, the address of the next instruction to be executed is stored in the stack area. When a subroutine is called, the address one before the next instruction to be executed is stored in the stack area. Fig. 8 Register push and pop at interrupt generation and subroutine call Table 4. Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP 3800 GROUP USER'S MANUAL 1-11 HARDWARE FUNCTIONAL DESCRIPTION Processor status register (PS) The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to "1", but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. (2) Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". (3) Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". When an interrupt occurs, this flag is automatically set to "1" to prevent other interrupts from interfering until the current interrupt is serviced. (4) Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. (5) Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". The saved processor status is the only place where the break flag is ever set. (6) Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. (7) Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds + 127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. (8) Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5. Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag -- -- I flag SEI CLI D flag SED CLD B flag -- -- T flag SET CLT V flag -- CLV N flag -- -- 1-12 3800 GROUP USER'S MANUAL HARDWARE FUNCTIONAL DESCRIPTION CPU mode register The CPU mode register is allocated at address 003B16. The CPU mode register contains the stack page selection bit. b7 b0 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page Not used (return "0" when read) Fig. 9 Structure of CPU mode register 3800 GROUP USER'S MANUAL 1-13 HARDWARE FUNCTIONAL DESCRIPTION Memory Special function register (SFR) area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Special page ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. RAM area RAM capacity (bytes) Address XXXX16 000016 SFR area 004016 010016 Zero page 192 256 384 512 640 768 896 1024 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 RAM XXXX16 Reserved area 044016 ROM area ROM capacity (bytes) Address YYYY16 Address ZZZZ16 Not used YYYY16 Reserved ROM area (128 bytes) 4096 8192 12288 16384 20480 24576 28672 32768 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 ZZZZ16 ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Special page Reserved ROM area Fig. 10 Memory map diagram 1-14 3800 GROUP USER'S MANUAL HARDWARE FUNCTIONAL DESCRIPTION 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Transmit/Receive buffer register (TB/RB) Serial I/O status register (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Interrupt control register 2(ICON2) Fig. 11 Memory map of special function register (SFR) 3800 GROUP USER'S MANUAL 1-15 HARDWARE FUNCTIONAL DESCRIPTION I/O Ports Direction registers The 3800 group has 58 programmable I/O pins arranged in eight I/O ports (ports P0 to P7). The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 6. List of I/O port functions Pin P00 - P07 Name Port P0 Input/Output Input/output, individual bits Input/output, individual bits Input/output, individual bits Input/output, individual bits I/O Format CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level Non-Port Function Address low-order byte output Address high-order byte output Related SFRs CPU mode register Ref.No. P10 - P17 Port P1 CPU mode register (1) P20 - P27 Port P2 Data bus I/O CPU mode register P30 - P37 P40,P41 P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK, P47/SRDY P50/INT2, P51/INT3, P52/INT4, P53/INT5 P54/CNTR0, P55/CNTR1 P56,P57 P60 - P67 Port P3 Control signal I/O CPU mode register Port P4 Input/output, individual bits CMOS 3-state output CMOS compatible input level External interrupt input Interrupt edge selection register Serial I/O control register UART control register (2) (3) (4) (5) (6) Serial I/O function I/O External interrupt input Port P5 Input/output, individual bits CMOS 3-state output CMOS compatible input level Interrupt edge selection register (2) Timer X and Timer Y function I/O Timer XY mode register (7) Port P6 Input/output, individual bits Input/output, individual bits P70, P71 Port P7 CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level (1) Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. 1-16 3800 GROUP USER'S MANUAL HARDWARE FUNCTIONAL DESCRIPTION (1) Ports P0, P1, P2, P3, P40, P41, P56, P57, P6, P7 Direction register (2) Ports P42, P43, P50 - P53 Direction register Data bus Port latch Data bus Port latch Interrupt input (3) Port P44 Serial I/O enable bit Receive enable bit Direction register (4) Port P45 P45/TXD P-channel output disable bit Serial I/O enable bit Transmit enable bit Direction register Data bus Port latch Data bus Port latch Serial I/O input Serial I/O output (5) Port P46 Serial I/O synchronous clock selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register (6) Port P47 Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register Data bus Port latch Data bus Port latch Serial I/O clock output Serial I/O external clock input Serial I/O ready output (7) Ports P54, P55 Direction register Data bus Port latch Pulse output mode Timer output Counter input Interrupt input Fig. 12 Port block diagram (single-chip mode) 3800 GROUP USER'S MANUAL 1-17 HARDWARE FUNCTIONAL DESCRIPTION Interrupts Interrupts occur by fifteen sources: eight external, six internal, and one software. Interrupt operation When an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag is set to inhibit other interrupts from interfering.The corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter. Interrupt control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. Notes on use When the active edge of an external interr upt (INT0 to INT5, CNTR0, or CNTR1) is changed, the corresponding interrupt request bit may also be set. Therefore, please take following sequence; (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear the interrupt request bit which is selected to "0". (4) Enable the external interrupt which is selected. Table 7. Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 INT1 Serial I/O reception Serial I/O transmission Timer X Timer Y Timer 1 Timer 2 CNTR0 CNTR1 INT2 INT3 INT4 INT5 BRK instruction Priority 1 2 3 4 Vector Addresses (Note 1) High Low FFFD16 FFFC16 FFFB16 FFF916 FFF716 FFFA16 FFF816 FFF616 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O data reception At completion of serial I/O transfer shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of INT5 input At BRK instruction execution Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O is selected 5 6 7 8 9 10 11 12 13 14 15 16 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDD16 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDC16 Valid when serial I/O is selected STP release timer underflow External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Non-maskable software interrupt Note 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 1-18 3800 GROUP USER'S MANUAL HARDWARE FUNCTIONAL DESCRIPTION Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 13 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit INT5 active edge selection bit Not used (return "0" when read) 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit INT4 interrupt request bit INT5 interrupt request bit Not used (return "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit b7 b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit INT4 interrupt enable bit INT5 interrupt enable bit Not used (return "0" when read) (Do not write "1" to this bit) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 14 Structure of interrupt-related registers 3800 GROUP USER'S MANUAL 1-19 HARDWARE FUNCTIONAL DESCRIPTION Timers The 3800 group has four timers: timer X, timer Y, timer 1, and timer 2. All timers are count down. When the timer reaches "0016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1". The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. Timer 1 and Timer 2 The count source of prescaler 12 is the oscillation frequency divided by 16. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. Timer X and Timer Y Timer X and Timer Y can each be selected in one of four operating modes by setting the timer XY mode register. Timer Mode The timer counts f(XIN)/16 in timer mode. Pulse Output Mode Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of the timer reach "0016", the signal output from the CNTR0 (or CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge switch bit is "0", output begins at " H". If it is "1", output starts at "L". When using a timer in this mode, set the corresponding port P54 ( or port P55) direction register to output mode. Event Counter Mode Operation in event counter mode is the same as in timer mode, except the timer counts signals input through the CNTR0 or CNTR1 pin. Pulse Width Measurement Mode If the CNTR0 (or CNTR1) active edge selection bit is "0", the timer counts at the oscillation frequency divided by 16 while the CNTR0 (or CNTR1) pin is at "H". If the CNTR0 (or CNTR1) active edge switch bit is "1", the count continues during the time that the CNTR0 (or CNTR1) pin is at "L". In all of these modes, the count can be stopped by setting the timer X (timer Y) count stop bit to "1". Every time a timer underflows, the corresponding interrupt request bit is set. b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bit b1b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bit b5b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop Fig. 15 Structure of timer XY register 1-20 3800 GROUP USER'S MANUAL HARDWARE FUNCTIONAL DESCRIPTION Data bus Oscillator f(XIN) Divider 1/16 Pulse width measurement mode P54/CNTR0 pin CNTR0 active edge switch bit "0" "1" Timer mode Pulse output mode Prescaler X (8) Event counter mode CNTR0 active edge switch bit "1" "0" Q Timer X count stop bit To CNTR0 interrupt request bit Timer X (8) To timer X interrupt request bit Prescaler X latch (8) Timer X latch (8) Q Toggle flip- flop R Timer X latch write pulse Pulse output mode Data bus T Port P54 direction register Port P54 latch Pulse output mode Prescaler Y latch (8) Pulse width measurement mode P55/CNTR1 pin CNTR1 active edge switch bit "0" "1" Timer mode Pulse output mode Prescaler Y (8) Event counter mode CNTR1 active edge switch bit "1" "0" Q Timer Y count stop bit Timer Y latch (8) Timer Y (8) To timer Y interrupt request bit To CNTR1 interrupt request bit Q Toggle flip- flop R Timer Y latch write pulse Pulse output mode T Port P55 direction register Port P55 latch Pulse output mode Data bus Prescaler 12 latch (8) Timer 1 latch (8) Timer 2 latch (8) Prescaler 12 (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit Fig. 16 Block diagram of timer X, timer Y, timer 1, and timer 2 3800 GROUP USER'S MANUAL 1-21 HARDWARE FUNCTIONAL DESCRIPTION Serial I/O Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Clock synchronous serial I/O mode Clock synchronous serial I/O mode can be selected by setting the mode selection bit of the serial I/O control register to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (address 001816). Data bus Serial I/O control register Address 001A16 Address 001816 Receive buffer P44/RXD Receive shift register Shift clock P46/SCLK1 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit f(XIN) XIN BRG count source selection bit 1/4 Serial I/O synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 Clock control circuit Shift clock Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 001916 1/4 P47/SRDY F/F Falling-edge detector P45/TXD Transmit shift register Transmit buffer Address 001816 Data bus Fig. 17 Block diagram of clock synchronous serial I/O Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY Write pulse to receive/transmit buffer (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2 : If data is written to the transmit buffer when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 18 Operation of clock synchronous serial I/O function 1-22 3800 GROUP USER'S MANUAL HARDWARE FUNCTIONAL DESCRIPTION Asynchronous serial I/O (UART) mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next character is being received. Data bus Address 001816 Receive buffer OE Character length selection bit P44/RXD STdetector 7 bits 8 bits PE FE SP detector Clock control circuit Serial I/O synchronous clock selection bit P46/SCLK BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 P45/TXD Character length selection bit Transmit buffer Address 001816 Data bus Transmit buffer empty flag (TBE) Serial I/O status register Address 001916 Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Receive shift register 1/16 UART control register Address 001B16 Serial I/O control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) f(XIN) Fig. 19 Block diagram of UART serial I/O 3800 GROUP USER'S MANUAL 1-23 HARDWARE FUNCTIONAL DESCRIPTION Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 TSC=1V Serial output TXD ST D0 D1 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 V SP Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 RBF=1 Serial input RXD ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 20 Operation of UART serial I/O function Serial I/O control register (SIOCON) 001A16 The serial I/O control register consists of eight control bits for the serial I/O function. UART control register (UARTCON) 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P45/TXD pin. spectively). Writing "0" to the serial I/O enable bit SIOE (bit 7 of the Serial I/O Control Register) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". Transmit buffer/Receive buffer register (TB/ RB) 001816 The transmit buffer and the receive buffer are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". Serial I/O status register (SIOSTS) 001916 The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, re- Baud rate generator (BRG) 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. 1-24 3800 GROUP USER'S MANUAL HARDWARE FUNCTIONAL DESCRIPTION b7 b0 Serial I/O status register (SIOSTS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b7 b0 Serial I/O control register (SIOCON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY output enable bit (SRDY) 0: P47 pin operates as ordinaly I/O pin 1: P47 pin operates as S RDY output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P44 to P47 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P44 to P47 operate as serial I/O pins) b7 b0 UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig. 21 Structure of serial I/O control registers 3800 GROUP USER'S MANUAL 1-25 HARDWARE FUNCTIONAL DESCRIPTION Reset Circuit To reset the microcomputer, the RESET pin should be held at an "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between 3.0 V and 5.5 V, and between 4.0 V and 5.5 V for extended operating temperature version), reset is released. Internal operation does not begin until after 8 to 13 XIN clock cycles are completed. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.6 V for VCC of 3.0 V (Extended operating temperature version: the reset input voltage is less than 0.8 V for VCC of 4.0 V). (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 direction register (5) Port P4 direction register (6) Port P5 direction register (7) Port P6 direction register (8) Port P7 direction register (9) Serial I/O status register (10) Serial I/O control register (11) UART control register Address (000116) * * * (000316) * * * (000516) * * * (000716) * * * (000916) * * * (000B16) * * * (000D16) * * * (000F16) * * * Register contents 0016 0016 0016 0016 0016 0016 0016 0016 (001916) * * * 1 0 0 0 0 0 0 0 (001A16) * * * 0016 (001B16) * * * 1 1 1 0 0 0 0 0 (002016) * * * (002116) * * * (002216) * * * (002316) * * * (002416) * * * (002516) * * * (002616) * * * (002716) * * * FF16 0116 FF16 0016 FF16 FF16 FF16 FF16 0016 3.0V (Note 1) Power source 0V voltage 0.6V (Note 2) (12) Prescaler 12 (13) Timer 1 (14) Timer 2 Reset input 0V voltage (15) Timer XY mode register (16) Prescaler X (17) Timer X (18) Prescaler Y (19) Timer Y Note 1 : Extended operating temperature version : 4.0V Note 2 : Extended operating temperature version : 0.8V 1 5 M51953AL 4 0.1 F VCC RESET (20) Interrupt edge selection register (003A16) * * * (21) CPU mode register (22) Interrupt request register 1 (23) Interrupt request register 2 (24) Interrupt control register 1 (003B16) * * * 0 0 0 0 0 0 V 0 (003C16) * * * (003D16) * * * (003E16) * * * (003F16) * * * 0016 0016 0016 0016 3 VSS (25) Interrupt control register 2 3800 group Fig. 22 Example of reset circuit (26) Processor status register (27) Program counter (PS) ! ! ! ! ! 1 ! ! (PCH) Contents of address FFFD16 (PCL) Contents of address FFFC16 Note. ! : Undefined V : The initial values of CM1 are determined by the level at the CNVSS pin. The contents of all other registers and RAM are undefined after a reset, so they must be initialized by software. Fig. 23 Internal status of microcomputer after reset 1-26 3800 GROUP USER'S MANUAL HARDWARE FUNCTIONAL DESCRIPTION XIN RESET RESETOUT (internal reset) SYNC Address ? ? ? ? ? FFFC FFFD ADH, ADL Reset address from the vector table Data XIN: 8 to 13 clock cycles ? ? ? ? ? ADL ADH Notes 1: f(XIN) and f() are in the relationship: f(XIN)=2 * f(). 2: A question mark (?) indicates an undefined status that depends on the previous status. Fig. 24 Timing of reset 3800 GROUP USER'S MANUAL 1-27 HARDWARE FUNCTIONAL DESCRIPTION Clock Generating Circuit An oscillation circuit can be formed by connecting a resonator between XIN and XOUT. To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. When the STP status is released, prescaler 12 and timer 1 will start counting and reset will not be released until timer 1 underflows, so set the timer 1 interrupt enable bit to "0" before the STP instruction is executed. Oscillation control Stop Mode If the STP instruction is executed, the internal clock stops at "H". Timer 1 is set to "0116" and prescaler 12 is set to "FF16". Oscillator restarts when an external interrupt is received, but the internal clock remains at "H" until timer 1 underflows. This allows time for the clock circuit oscillation to stabilize. If oscillator is restarted by a reset, no wait time is generated, so keep the RESET pin at "L" level until oscillation has stabilized. Wait Mode If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator itself does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to "1" before the STP or WIT instruction is executed. XIN XOUT CIN COUT Fig. 25 Ceramic resonator circuit XIN XOUT Open External oscillation circuit Vcc Vss Fig. 26 External clock input circuit Interrupt request Interrupt disable flag (I) Reset STP instruction S Q S Q Q S Reset R WIT instruction R R STP instruction output ONW pin Single-chip mode 1/2 Rd Internal clock ONW control 1/8 Prescaler 12 FF16 0116 Timer 1 Reset or STP instruction Rf XIN XOUT Fig. 27 Block diagram of clock generating circuit 1-28 3800 GROUP USER'S MANUAL HARDWARE FUNCTIONAL DESCRIPTION Processor Modes Single-chip mode, memory expansion mode, and microprocessor mode can be selected by changing the contents of the processor mode bits CM0 and CM1 (bits 0 and 1 of address 003B16). In memory expansion mode and microprocessor mode, memory can be expanded externally through ports P0 to P3. In these modes, ports P0 to P3 lose their I/O port functions and become bus pins. Table 8. Functions of ports in memory expansion mode and microprocessor mode Port Name Function Port P0 Outputs low-order byte of address. Port P1 Outputs high-order byte of address. Operates as I/O pins for data D7 to D0 Port P2 (including instruction codes). P30 and P31 function only as output pins (except that the port latch cannot be read). P32 is the ONW input pin. P33 is the RESETOUT output pin. (Note) Port P3 P34 is the output pin. P35 is the SYNC output pin. P36 is the WR output pin, and P37 is the RD output pin. 000016 000816 004016 SFR area Internal RAM reserved area 000016 000816 004016 SFR area Internal RAM reserved area 044016 V 044016 YYYY16 FFFF16 Internal ROM FFFF16 Microprocessor mode The shaded areas are external memory areas. V : YYYY16 is the start address of internal ROM. Memory expansion mode Fig. 28 Memory maps in various processor modes Note: If CNVSS is connected to VSS, the microcomputer goes to single-chip mode after a reset, so this pin cannot be used as the RESETOUT output pin. Single-Chip Mode Select this mode by resetting the microcomputer with CNVSS connected to VSS. Memory Expansion Mode Select this mode by setting the processor mode bits to "01" in software with CNVSS connected to VSS. This mode enables external memory expansion while maintaining the validity of the internal ROM. Internal ROM will take precedence over external memory if addresses conflict. Microprocessor Mode Select this mode by resetting the microcomputer with CNVSS connected to VCC, or by setting the processor mode bits to "10" in software with CNVSS connected to VSS. In microprocessor mode, the internal ROM is no longer valid and external memory must be used. b7 b0 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page Not used (return "0" when read) Fig. 29 Structure of CPU mode register 3800 GROUP USER'S MANUAL 1-29 HARDWARE FUNCTIONAL DESCRIPTION Bus control with memory expansion The 3800 group has a built-in ONW function to facilitate access to external memory and I/O devices in memory expansion mode or microprocessor mode. If an "L" level signal is input to the ONW pin when the CPU is in a read or write state, the corresponding read or write cycle is extended by one cycle of . During this extended period, the RD or WR signal remains at "L". This extension period is valid only for writing to and reading from addresses 000016 to 000716 and 044016 to FFFF16 in microprocessor mode, 004016 to YYYY16 in memory expansion mode, and only read and write cycles are extended. Read cycle Dummy cycle Write cycle Read cycle Dummy cycle Write cycle AD15 to AD0 RD WR ONW V V V V : Period during which ONW input signal is received During this period, the ONW signal must be fixed at either "H" or "L". At all other times, the input level of the ONW signal has no affect on operations. The bus cycles is not extended for an address in the area 000816 to 043F16, regardless of whether the ONW signal is received. Fig. 30 ONW function timing 1-30 3800 GROUP USER'S MANUAL HARDWARE NOTES ON PROGRAMMING NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1". After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to "1". Serial I/O continues to output the final bit from the TXD pin after transmission is completed. Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before executing a BBC or BBS instruction. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock is half of the XIN frequency. When the ONW function is used in modes other than single-chip mode, the frequency of the internal clock may be one fourth the XIN frequency. Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC. Memory Expansion Mode and Microprocessor Mode Execute the LDM or STA instruction for writing to port P3 (address 000616) in memory expansion mode and microprocessor mode. Set areas which can be read out and write to port P3 (address 000616) in a memory, using the read-modify-write instruction (SEB, CLB). Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1). Multiplication and Division Instructions The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direction registers. 3800 GROUP USER'S MANUAL 1-31 HARDWARE DATA REQUIRED FOR MASK ORDERS/ROM PROGRAMMING METHOD DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1. Mask ROM Order Confirmation Form 2. Mark Specification Form 3. Data to be written to ROM, in EPROM form (three identical copies) ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 9. Programming adapter Package 64P4B, 64S1B 64P6N-A 64D0 Name of Programming Adapter PCA4738S-64A PCA4738F-64A PCA4738L-64A The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 31 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours. Fig. 31 Programming and testing of One Time PROM version 1-32 3800 GROUP USER'S MANUAL HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT FUNCTIONAL DESCRIPTION SUPPLEMENT Interrupt 3800 group permits interrupts on the basis of 15 sources. It is vector interrupts with a fixed priority system. Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. This priority is determined Table 10. Interrupt sources, vector addresses and interrupt priority Vector addresses Priority Interrupt sources High-order 1 2 Reset (Note) INT0 interrupt FFFD16 FFFB16 Low-order FFFC16 FFFA16 Non-maskable External interrupt (active edge selectable) 3 INT1 interrupt FFF916 FFF816 External interrupt (active edge selectable) 4 5 6 7 8 9 10 Serial I/O receive interrupt Serial I/O transmit interrupt Timer X interrupt Timer Y interrupt Timer 1 interrupt Timer 2 interrupt CNTR0 interrupt FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 External interrupt (active edge selectable) 11 CNTR1 interrupt FFE916 FFE816 External interrupt (active edge selectable) 12 INT2 interrupt FFE716 FFE616 External interrupt (active edge selectable) 13 INT3 interrupt FFE516 FFE416 External interrupt (active edge selectable) 14 INT4 interrupt FFE316 FFE216 External interrupt (active edge selectable) 15 INT5 interrupt FFE116 FFE016 External interrupt (active edge selectable) 16 BRK instruction interrupt FFDD16 FFDC16 Non-maskable software interrupt STP release timer underflow Valid when serial I/O is selected Valid when serial I/O is selected Remarks by hardware, but variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. For interrupt sources, vector addresses and interrupt priority, refer to "Table 10." Note: Reset functions in the same way as an interrupt with the highest priority. 3800 GROUP USER'S MANUAL 1-33 HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT Timing After Interrupt The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. Figure 32 shows a timing chart after an interrupt occurs, and Figure 33 shows the time up to execution of the interrupt processing routine. SYNC RD WR Address bus Data bus PC Not used S, SPS S-1, SPS S-2, SPS BL AL BH AL, AH AH PCH PCL PS SYNC : CPU operation code fetch cycle BL, BH : Vector address of each interrupt AL, AH : Jump destination address of each interrupt SPS : "0016" or "0116" Fig. 32 Timing chart after an interrupt occurs Generation of interrupt request Start of interrupt processing Main routine Waiting time for post-processing of pipeline Stack push and Vector fetch Interrupt processing routine 0 to 16 T cycles 2 cycles 5 cycles 7 to 23 cycles (At performing 8.0 MHz, 1.75 s to 5.75 s) T : at execution of DIV instruction (16 cycles) Fig. 33 Time up to execution of the interrupt processing routine 1-34 3800 GROUP USER'S MANUAL CHAPTER 2 APPLICATION 2.1 2.2 2.3 2.4 2.5 I/O port Timer Serial I/O Processor mode Reset APPLICATION 2.1 I/O port 2.1 I/O port 2.1.1 Memory map of I/O port 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Fig. 2.1.1 Memory map of I/O port related registers 2-2 3800 GROUP USER'S MANUAL APPLICATION 2.1 I/O port 2.1.2 Related registers Port Pi b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6, 7) [Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16] B 0 Port Pi0 1 Port Pi1 Name q Function In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins (Note) At reset RW ? ? ? ? ? ? ? ? q 2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7 Note : Port P7 register [Address : 0E16] Port P7 is a 2-bit port (P70, P71). Accordingly, when bits 2 to 7 are read out, the contents are "0." Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 7) Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i =0, 1, 2, 3, 4, 5, 6, 7) [Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16, 0F16] B Name Function 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode (Note) (Note) (Note) (Note) (Note) (Note) At reset RW ! ! ! ! ! ! ! ! 0 Port Pi direction register 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Note : Port P7 direction register [Address : 0F16] Port P7 is a 2-bit port (P70, P71). Accordingly, these bits do not have a direction register function. Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6, 7) 3800 GROUP USER'S MANUAL 2-3 APPLICATION 2.1 I/O port 2.1.3 Handling of unused pins Table 2.1.1 Handling of unused pins (in single-chip mode) Name of Pins/Ports P0, P1, P2, P3, P4, P5, P6, P7 Handling * Set to the input mode and connect to VCC or VSS through a resistor of 1 k to 10 k . * Set to the output mode and open at "L" or "H." Open (only when using external clock). XOUT Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode) Name of Pins/Ports P30, P31 P4, P5, P6, P7 Handling Open * Set to the input mode and connect to VCC or VSS through a resistor of 1 k to 10 k . * Set to the output mode and open at "L" or "H." Connect to VCC through a resistor of 1 k to 10 k . Open Open Open Open (only when using external clock). ONW RESETOUT SYNC XOUT 2-4 3800 GROUP USER'S MANUAL APPLICATION 2.2 Timer 2.2 Timer 2.2.1 Memory map of timer 002016 002116 002216 002316 002416 002516 002616 002716 003C16 003D16 003E16 003F16 Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Fig. 2.2.1 Memory map of timer related registers 3800 GROUP USER'S MANUAL 2-5 APPLICATION 2.2 Timer 2.2.2 Related registers Prescaler 12, Prescaler X, Prescaler Y b7 b6 b5 b4 b3 b2 b1 b0 Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY) [Address : 2016, 2416, 2616] B 0 1 2 3 4 5 6 7 Function q q q At reset RW The count value of each prescaler is set. The value set in this register is written to both the prescaler and the prescaler latch at the same time. When the prescaler is read out, the value (count value) of the prescaler is read out. 1 1 1 1 1 1 1 1 Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y Timer 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1) [Address : 2116] B 0 1 2 3 4 5 6 7 Function q q q At reset RW The count value of the Timer 1 is set. The value set in this register is written to both the Timer 1 and the Timer 1 latch at the same time. When the Timer 1 is read out, the value (count value) of the Timer 1 is read out. 1 0 0 0 0 0 0 0 Fig. 2.2.3 Structure of Timer 1 2-6 3800 GROUP USER'S MANUAL APPLICATION 2.2 Timer Timer 2, Timer X, Timer Y b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2), Timer X (TX), Timer Y (TY) [Address : 2216, 2516, 2716] B 0 1 2 3 4 5 6 7 q q q Function The count value of each timer is set. The value set in this register is written to both the Timer and the Timer latch at the same time. When the Timer is read out, the value (count value) of the Timer is read out. At reset RW 1 1 1 1 1 1 1 1 Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y 3800 GROUP USER'S MANUAL 2-7 APPLICATION 2.2 Timer Timer XY mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer XY mode register (TM) [Address : 2316] Name B 0 Timer X operating mode bit Function b1 b0 At reset RW 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 1 : Pulse width measurement mode 2 CNTR0 active edge switch bit It depends on the operating mode of the Timer X (refer to Table 2.2.1). 0 : Count start 3 Timer X count stop bit 1 : Count stop 0 0 0 0 0 0 0 0 4 Timer Y operating mode bit 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 5 1 1 : Pulse width measurement mode 6 CNTR1 active edge switch bit It depends on the operating mode of the Timer Y (refer to Table 2.2.1). Timer Y count stop bit 0 : Count start 7 1 : Count stop b5 b4 Fig. 2.2.5 Structure of Timer XY mode register Table. 2.2.1 Function of CNTR0/CNTR1 edge switch bit Operating mode of Timer X/Timer Y Timer mode Function of CNTR0/CNTR1 edge switch bit (bits 2 and 6) "0" "1" Pulse output mode "0" "1" Event counter mode "0" "1" Pulse width measurement mode "0" "1" * Generation of CNTR0/CNTR1 interrupt request : Falling (No effect on timer count) * Generation of CNTR0/CNTR1 interrupt request : Rising (No effect on timer count) * Start of pulse output : From "H" level * Generation of CNTR0/CNTR1 interrupt request : Falling * Start of pulse output : From "L" level * Generation of CNTR0/CNTR1 interrupt request : Rising * Timer X/Timer Y : Count of rising edge * Generation of CNTR0/CNTR1 interrupt request : Falling * Timer X/Timer Y : Count of falling edge * Generation of CNTR0/CNTR1 interrupt request : Rising * Timer X/Timer Y : Measurement of "H" level width * Generation of CNTR0/CNTR1 interrupt request : Falling * Timer X/Timer Y : Measurement of "L" level width * Generation of CNTR0/CNTR1 interrupt request : Rising edge edge edge edge edge edge edge edge 2-8 3800 GROUP USER'S MANUAL APPLICATION 2.2 Timer Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 1 (IREQ1) [Address : 3C16] B Name Function 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request At reset RW T T T T T T T T 0 INT0 interrupt request bit 1 INT1 interrupt request bit 2 Serial I/O receive interrupt request bit 0 0 0 0 0 0 0 0 3 Serial I/O transmit interrupt request bit bit 4 Timer X interrupt request 5 Timer Y interrupt request bit 6 Timer 1 interrupt request bit 7 Timer 2 interrupt request bit 0 : No interrupt request 1 : Interrupt request T "0" is set by software, but not "1." Fig. 2.2.6 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address : 3D16] B Name Function 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request At reset RW T T T T T T ! ! 0 CNTR0 interrupt request bit 1 CNTR1 interrupt request bit 2 INT2 interrupt request bit 3 INT3 interrupt request bit 4 5 6 7 0 0 0 0 0 0 0 0 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request INT4 interrupt request bit 1 : Interrupt request 0 : No interrupt request INT5 interrupt request bit 1 : Interrupt request Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0." T "0" is set by software, but not "1." Fig. 2.2.7 Structure of Interrupt request register 2 3800 GROUP USER'S MANUAL 2-9 APPLICATION 2.2 Timer Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 INT0 interrupt enable bit 1 INT1 interrupt enable bit enable bit 3 Serial I/O transmit interrupt enable bit 4 Timer X interrupt enable bit 0 0 0 0 0 0 0 0 2 Serial I/O receive interrupt 5 Timer Y interrupt enable bit 6 Timer 1 interrupt enable bit 7 Timer 2 interrupt enable bit Fig. 2.2.8 Structure of Interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 00 Interrupt control reigster 2 (ICON2) [Address : 3F16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 CNTR0 interrupt enable bit 1 CNTR1 interrupt enable bit 2 INT2 interrupt enable bit 3 INT3 interrupt enable bit 4 INT4 interrupt enable bit 5 INT5 interrupt enable bit 6 Fix these bits to "0." 7 0 0 0 0 0 0 0 0 Fig. 2.2.9 Structure of Interrupt control register 2 2-10 3800 GROUP USER'S MANUAL APPLICATION 2.2 Timer 2.2.3 Timer application examples (1) Basic functions and uses [Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2) The Timer count stop bit is set to "0" after setting a count value to a timer. Then a timer interrupt request occurs after a certain period. [Use] * Generation of an output signal timing * Generation of a waiting time [Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer 1, Timer 2) The value of a timer latch is automatically written to a corresponding timer every time a timer underflows, and each cyclic timer interrupt request occurs. [Use] * Generation of cyclic interrupts * Clock function (measurement of 250m second) * Control of a main routine cycle Application example 1 [Function 3] Output of Rectangular waveform (Timer X, Timer Y) The output level of the CNTR pin is inverted every time a timer underflows (Pulse output mode). [Use] * A piezoelectric buzzer output Application example 2 * Generation of the remote-control carrier waveforms [Function 4] Count of External pulse (Timer X, Timer Y) External pulses input to the CNTR pin are selected as a timer count source (Event counter mode). [Use] * Measurement of frequency Application example 3 * Division of external pulses. * Generation of interrupts in a cycle based on an external pulse. (count of a reel pulse) [Function 5] Measurement of External pulse width (Timer X, Timer Y) The "H" or "L" level width of external pulses input to CNTR pin is measured (Pulse width measurement mode). [Use] * Measurement of external pulse frequency (Measurement of pulse width of FG pulse V generated by motor) Application example 4 * Measurement of external pulse duty (when the frequency is fixed) VFG pulse : Pulse used for detecting the motor speed to control the motor speed. 3800 GROUP USER'S MANUAL 2-11 APPLICATION 2.2 Timer (2) Timer application example 1 : Clock function (measurement of 250 ms) Outline : The input clock is divided by a timer so that the clock counts up every 250 ms. Specifications : * The clock f(XIN) = 4.19 MHz (2 22 Hz) is divided by a timer. * The clock is counted at intervals of 250 ms by the Timer X interrupt. Figure 2.2.10 shows a connection of timers and a setting of division ratios, Figures 2.2.11 show a setting of related registers, and Figure 2.2.12 shows a control procedure. Fixed Prescaler X Timer X Timer X interrupt request bit The clock is divided by 4 by software. f(XIN) = 4.19 MHz 1/16 1/256 1/256 0 or 1 250 ms 1/4 1 second 0 : No interrupt request 1 : Interrupt request Fig. 2.2.10 Connection of timers and setting of division ratios [Clock function] 2-12 3800 GROUP USER'S MANUAL APPLICATION 2.2 Timer Timer XY mode register (Address : 2316) b7 b0 TM 1 00 Timer X operating mode bits : Timer mode Timer X count stop bit : Count stop Set to "0" at starting to count. Prescaler X (Address : 2416) b7 b0 PREX b7 255 Timer X (Address:2516) b0 Set "division ratio - 1" TX 255 Interrupt control register 1 (Address : 3E16) b7 b0 ICON1 1 Timer X interrupt enable bit : Interrupt enabled Interrupt request register 1 (Address : 3C16) b7 b0 IREQ1 0 Timer X interrupt request bit (becomes "1" every 250 ms) Fig. 2.2.11 Setting of related registers [Clock function] 3800 GROUP USER'S MANUAL 2-13 APPLICATION 2.2 Timer Control procedure : Figure 2.2.12 shows a control procedure. RESET q X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded. Initialization SEI TM XXXX1X002 (Address : 2316) ICON1 (Address : 3E16), bit4 1 PREX (Address : 2416) TX (Address : 2516) TM CLI q All interrupts : Disabled Timer X : Timer mode Timer X interrupt : Enabled Set "division ratio - 1" to the Prescaler X and Timer X. Timer X count : Operating Interrupts : Enabled Main processing [Processing for completion of setting clock] (Note 1) PREX (Address : 2416) TX (Address : 2516) IREQ1 (Address : 3C16), bit4 Fig. 2.2.12 Control procedure [Clock function] .... q q .... 256 - 1 256 - 1 0 q .... (Address : 2316), bit3 q .... q .... q 256 - 1 256 - 1 0 When restarting the clock from zero second after completing to set the clock, re-set timers. Note 1: This processing is performed only at completing to set the clock. Timer X interrupt processing routine CLT (Note 2) CLD (Note 3) Push register to stack Note 2: When using the Index X mode flag (T). Note 3: When using the Decimal mode flag (D). q Push the register used in the interrupt processing routine into the stack. Clock stop? N Clock count up (1/4 second-year) Y q Check if the clock has already been set. q Count up the clock. Pop registers q Pop registers which is pushed to stack RTI 2-14 3800 GROUP USER'S MANUAL APPLICATION 2.2 Timer (3) Timer application example 2 : Piezoelectric buzzer output Outline : The rectangular waveform output function of a timer is applied for a piezoelectric buzzer output. Specifications : * The rectangular waveform resulting from dividing clock f(XIN) = 4.19 MHz into about 2 kHz (2048 Hz) is output from the P54/CNTR0 pin. * The level of the P54/CNTR0 pin fixes to "H" while a piezoelectric buzzer output is stopped. Figure 2.2.13 shows an example of a peripheral circuit, and Figure 2.2.14 shows a connection of the timer and setting of the division ratio. The "H" level is output while a piezoelectric buzzer output is stopped. CNTR0 output 3800 group P54/CNTR0 PiPiPi.... 244 s 244 s Set a division ratio so that the underflow output cycle of the Timer X becomes this value. Fig. 2.2.13 Example of a peripheral circuit Fixed f(XIN) = 4.19 MHz Prescaler X Timer X Fixed 1/16 1 1/64 1/2 CNTR0 Fig. 2.2.14 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output] 3800 GROUP USER'S MANUAL 2-15 APPLICATION 2.2 Timer Timer XY mode register (Address : 2316) b7 b0 TM 1001 Timer X operating mode bits : Pulse output mode CNTR0 active edge switch bit : Output from the "H" level Timer X count stop bit : Count stop Set to "0" at starting to count. Timer X (Address : 2516) b7 b0 TX 63 Prescaler X (Address : 2416) b7 b0 Set "division ratio - 1" PREX 0 Fig. 2.2.15 Setting of related registers [Piezoelectric buzzer output] Control procedure : Figure 2.2.16 shows a control procedure. RESET Initialization P5 P5D .... .... qX : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded. 1 (Address : 0A16), bit4 XXX1XXXX2 (Address : 0B16) q 0 ICON1 (Address : 3E16), bit4 XXXX10012 (Address : 2316) TM (Address : 2516) TX 64 - 1 PREX (Address : 2416) 1-1 .... q q Timer X interrupts : Disabled The CNTR0 output is stopped at this point (stop outputting a piezoelectric buzzer). Set "division ratio - 1" to the Prescaler X and Timer X. Main processing The piezoelectric buzzer request occured in the main processing is processed in the output unit. Output unit q A piezoelectric buzzer is requested? N Y TM (Address : 2316), bit3 TX (Address : 2516) 1 64 -1 TM (Address : 2316 ), bit3 0 During stopping outputting a piezoelectric buzzer During outputting a piezoelectric buzzer Fig. 2.2.16 Control procedure [Piezoelectric buzzer output] 2-16 3800 GROUP USER'S MANUAL APPLICATION 2.2 Timer (4) Timer application example 3 : Measurement of frequency Outline : The following two values are compared for judging if the frequency is within a certain range. * A value counted a pulse which is input to P55/CNTR1 pin by a timer. * A referance value Specifications : * The pulse is input to the P55/CNTR1 pin and counted by the Timer Y. * A count value is read out at the interval of about 2 ms (Timer 1 interrupt interval : 244 s ! 8). When the count value is 28 to 40, it is regarded the input pulse as a valid. * Because the timer is a down-counter, the count value is compared with 227 to 215V . V 227 to 215 = 255 (initialized value of counter) - 28 to 40 (the number of valid value). Figure 2.2.17 shows a method for judging if input pulse exists, and Figure 2.2.18 shows a setting of related registers. Input pulse **** **** **** 71.4 s or more (14 kHz or less) Invalid 2 ms 71.4 s 71.4 s (14 kHz) Valid = 28 counts 50 s(20 kHz) 50 s or less (20 kHz or more) Invalid 2 ms 50 s = 40 counts Fig 2.2.17 A method for judging if input pulse exists 3800 GROUP USER'S MANUAL 2-17 APPLICATION 2.2 Timer Timer XY mode register (Address : 2316) b7 b0 TM 1110 Timer Y operating mode bit : Event counter mode CNTR1 active edge switch bits : Count at falling edge Timer Y count stop bit : Count stop Set to "0" at starting to count. Prescaler 12 (Address : 2016) b7 b0 PRE12 63 Timer 1 (Address : 2116) b7 b0 T1 7 Set "division ratio - 1" Prescaler Y (Address : 2616) b7 b0 PREY 0 Timer Y (Address : 2716) b7 b0 TY 255 Set "255" to this register immediately before counting pulse. (After a certain time, this value is decreased by the number of input pulses) Interrupt control register 1 (Address : 3E16) b7 b0 ICON1 10 Timer Y interrupt enable bit : Interrupt disabled Timer 1 interrupt enable bit : Interrupt enabled Interrupt request register 1 (Address : 3C16) b7 b0 IREQ1 0 Judgment of Timer Y interrupt request bit (When this bit is set to "1" at reading out the count value of the Timer Y (address : 2716), 256 pulses or more are input (at setting 255 to the Timer Y).) Fig. 2.2.18 Setting of related registers [Measurement of frequency] 2-18 3800 GROUP USER'S MANUAL APPLICATION 2.2 Timer Control procedure : Figure 2.2.19 shows a control procedure. RESET Initialization SEI (Address : 2316) 1110XXXX2 TM PRE12 (Address : 2016) 64-1 (Address : 2116) T1 8-1 PREY (Address : 2616) 1-1 (Address : 2716) TY 256-1 ICON1 (Address : 3E16), bit6 1 TM .... (Address : 2316), bit7 0 .... .... q X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded. q All interrupts : Disabled Timer Y : Event counter mode (Count at falling edge of pulse input from CNTR1 pin) Set the division ratio so that the Timer 1 interrupt occurs every 2 ms. Timer 1 interrupt : Enabled Timer Y count : Start Interrupts : Enabled q q q q CLI q Timer 1 interrupt processing routine CLT (Note 1) CLD (Note 2) Push register to stack q Note 1: When using the Index X mode flag (T). Note 2: When using the Decimal mode flag (D). Push the register used in the interrupt processing routine into the stack. 1 IREQ1 (Address : 3C 16), bit5? 0 (A) TY (Address : 27 16) q When the count value is 256 or more, the processing is performed as out of range. q q Read the count value. Store the count value in the accumulator (A). 214 < (A) < 228? Out of range Fpulse 0 In range q q Compare the count value read with the reference value. Store the comparison result in flag Fpulse. 1 Fpulse TY (Address : 2716) IREQ1 (Address : 3C 16), bit5 256 - 1 0 q q Initialize the count value. Set the Timer Y interrupt request bit to "0." Processing for a result of judgment Pop registers q Pop registers which is pushed to stack. RTI Fig. 2.2.19 Control procedure [Measurement of frequency] 3800 GROUP USER'S MANUAL 2-19 APPLICATION 2.2 Timer (5) Timer application example 4 : Measurement of pulse width of FG pulse generated by motor Outline : The "H" level width of a pulse input to the P54/CNTR0 pin is counted by Timer X. An underflow is detected by Timer X interrupt and an end of the input pulse "H" level is detected by CNTR0 interrupt. Specifications : * The "H" level width of a FG pulse input to the P54/CNTR0 pin is counted by Timer X. (Example : When the clock frequency is 4.19 MHz, the count source would be 3.8 s that is obtained by dividing the clock frequency by 16. Measurement can be made up to 250 ms in the range of FFFF16 to 000016.) Figure 2.2.20 shows a connection of the timer and a setting of the division ratio, and Figure 2.2.21 shows a setting of related registers. Fixed f(XIN) = 4.19 MHz Prescaler X Timer X Timer X interrupt request bit 1/16 1/256 1/256 0 or 1 250 ms 0 : No interrupt request 1 : Interrupt request Fig. 2.2.20 Connection of the timer and setting of the division ratio [Measurement of pulse width] 2-20 3800 GROUP USER'S MANUAL APPLICATION 2.2 Timer Timer XY mode register (Address : 2316) b7 b0 TM 10 11 Timer X operating mode bits : Pulse width measurement mode CNTR0 active edge switch bit : Count "H" level width Timer X count stop bit : Count stop Set to "0" at starting to count. Prescaler X (Address : 2416) b7 b0 PREX 255 Timer X (Address : 2516) b7 b0 Set "division ratio - 1" TX 255 Interrupt control register 1 (Address : 3E16) b7 b0 ICON1 1 Timer X interrupt enable bit : Interrupt enabled Interrupt request register (Address : 3C16) b7 b0 IREQ1 0 Timer X interrupt request bit (This bit is set to "1" at underflow of Timer X.) Interrupt control register 2 (Address : 3F16) b7 b0 ICON2 1 CNTR0 interrupt enable bit : Interrupt enabled Interrupt request register 2 (Address : 3D16) b7 b0 IREQ2 0 CNTR0 interrupt request bit (This bit is set to "1" at completion of inputting "H" level signal.) Fig. 2.2.21 Setting of related registers [Measurement of pulse width] 3800 GROUP USER'S MANUAL 2-21 APPLICATION 2.2 Timer Figure 2.2.22 shows a control procedure. RESET Initialization SEI XXXX10112 (Address : 2316) TM 256-1 PREX (Address : 2416) 256-1 (Address : 2516) TX 1 ICON1 (Address : 3E16), bit4 0 IREQ1 (Address : 3C16), bit4 1 ICON2 (Address : 3F16), bit0 0 IREQ2 (Address : 3D16), bit0 TM .... (Address : 2316), bit3 0 .... .... CLI Timer X interrupt processing routine Processing for error RTI CNTR0 interrupt processing routine CLT (Note 1) CLD (Note 2) Push register to stack (A) Result of pulse width measurement low-order 8-bit (A) Result of pulse width measurement high-order 8-bit PREX (Address : 2416) TX (Address : 2516) PREX Inversion of (A) TX Inversion of (A) 256 - 1 256 - 1 q X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded. q q q q q All interrupts : Disabled Timer X : Pulse width measurement mode (Count "H" level width of pulse input from CNTR0 pin.) Set the division ratio so that the Timer X interrupt occurs every 250 ms. Timer X interrupt : Enabled CNTR0 interrupt : Enabled q Timer X count : Start Interrupts : Enabled q q Error occurs q Note 1: When using the Index X mode flag (T). Note 2: When using the Decimal mode flag (D). Push the register used in the interrupt processing routine into the stack. q A count value is read out and stored to RAM. q Set the division ratio so that the Timer X interrupt occurs every 250 ms. Pop registers q Pop registers which is pushed to stack. RTI Fig. 2.2.22 Control procedure [Measurement of pulse width] 2-22 3800 GROUP USER'S MANUAL APPLICATION 2.3 Serial I/O 2.3 Serial I/O 2.3.1 Memory map of serial I/O 001816 001916 001A16 001B16 001C16 003A16 003C16 003D16 003E16 003F16 Transmit/Receive buffer register (TB/RB) Serial I/O status register (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) Interrupt edge selection register (INTEDGE) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Fig. 2.3.1 Memory map of serial I/O related registers 3800 GROUP USER'S MANUAL 2-23 APPLICATION 2.3 Serial I/O 2.3.2 Related registers Transmit/Receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 Transmit/Receive buffer register (TB/RB) [Address : 1816] B Function from this buffer register. * At writing : a data is written to the Transmit buffer register. * At reading : a content of the Receive buffer register is read out. At reset RW 0 A transmission data is written to or a receive data is read out 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? Note : A content of the Transmit buffer register cannot be read out. A data cannot be written to the Receive buffer register. Fig. 2.3.2 Structure of Transmit/Receive buffer register Serial I/O status register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O status reigster (SIOSTS) [Address : 1916] Name B Transmit buffer empty flag 0 (TBE) Function 0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error 0 : (OE) (PE) (FE) = 0 1 : (OE) (PE) (FE) = 1 At reset 0 0 0 0 0 0 0 1 RW ! ! ! ! ! ! ! ! 1 Receive buffer full flag (RBF) 2 Transmit shift register shift completion flag (TSC) 3 Overrun error flag (OE) 4 Parity error flag (PE) 5 Framing error flag (FE) 6 Summing error flag (SE) 7 Nothing is allocated for this bit. It is a write disabled bit. When this bit is read out, the value is "0." Fig. 2.3.3 Structure of Serial I/O status register 2-24 3800 GROUP USER'S MANUAL APPLICATION 2.3 Serial I/O Serial I/O control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register (SIOCON) [Address : 1A16] Name B BRG count source 0 selection bit (CSS) Function 0 : f(XIN) 1 : f(XIN)/4 At selecting clock synchronous serial I/O 0 : BRG output divided by 4 1 : External clock input At selecting UART 0 : BRG output divided by 16 1 : External clock input divided by 16 At reset RW 0 0 1 Serial I/O synchronous clock selection bit (SCS) 2 SRDY output enable bit (SRDY) 3 Transmit interrupt source selection bit (TIC) 4 Transmit enable bit (TE) 5 Receive enable bit (RE) 6 Serial I/O mode selection bit (SIOM) 7 Serial I/O enable bit (SIOE) 0 : I/O port (P47) 1 : SRDY output pin 0 : Transmit buffer empty 1 : Transmit shift operating completion 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : UART 1 : Clock synchronous serial I/O 0 : Serial I/O disabled (P44-P47 : I/O port) 1 : Serial I/O enabled (P44-P47 : Serial I/O function pin) 0 0 0 0 0 0 Fig. 2.3.4 Structure of Serial I/O control register UART control register b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UARTCON) [Address : 1B16] B Name Character length 0 1 2 3 4 Function At reset RW 5 6 7 0 : 8 bits selection bit (CHAS) 1 : 7 bits 0 : Parity checking disabled Parity enable bit (PARE) 1 : Parity checking enabled 0 : Even parity Parity selection bit (PARS) 1 : Odd parity 0 : 1 stop bit Stop bit length selection bit (STPS) 1 : 2 stop bits In output mode P45/TxD P-channel 0 : CMOS output output disable bit 1 : N-channel open-drain (POFF) output Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "1." 0 0 0 0 0 1 1 1 5 5 5 Fig. 2.3.5 Structure of UART control register 3800 GROUP USER'S MANUAL 2-25 APPLICATION 2.3 Serial I/O Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator (BRG) [Address : 1C16] Function B A count value of Baud rate generator is set. 0 1 2 3 4 5 6 7 At reset RW ? ? ? ? ? ? ? ? Fig. 2.3.6 Structure of Baud rate generator Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A16] Name B 0 INT0 interrupt edge selection bit Function 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active At reset RW 0 0 0 0 0 0 0 5 5 0 1 INT1 interrupt edge selection bit 2 INT2 interrupt edge 3 selection bit INT3 interrupt edge selection bit 4 INT4 interrupt edge 5 6 7 selection bit 0 : Falling edge active INT5 interrupt edge 1 : Rising edge active selection bit Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0." Fig. 2.3.7 Structure of Interrupt edge selection register 2-26 3800 GROUP USER'S MANUAL APPLICATION 2.3 Serial I/O Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 1 (IREQ1) [Address : 3C16] B Name Function 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request At reset RW T T T T T T T T 0 INT0 interrupt request bit 1 INT1 interrupt request bit 2 Serial I/O receive interrupt request bit 3 Serial I/O transmit interrupt request bit 0 0 0 0 0 0 0 0 4 Timer X interrupt request bit bit 5 Timer Y interrupt request bit 6 Timer 1 interrupt request bit 7 Timer 2 interrupt request bit T "0" is set by software, but not "1." Fig. 2.3.8 Structure of Interrupt request register 1 Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 INT0 interrupt enable bit 1 INT1 interrupt enable bit 2 Serial I/O receive interrupt enable bit Serial I/O transmit interrupt 3 enable bit 0 0 0 0 0 0 0 0 4 Timer X interrupt enable bit 5 Timer Y interrupt enable bit 6 Timer 1 interrupt enable bit 7 Timer 2 interrupt enable bit Fig. 2.3.9 Structure of Interrupt control register 1 3800 GROUP USER'S MANUAL 2-27 APPLICATION 2.3 Serial I/O 2.3.3 Serial I/O connection examples (1) Control of peripheral IC equipped with CS pin There are connection examples using a clock synchronous serial I/O mode. Figure 2.3.10 shows connection examples of a peripheral IC equipped with the CS pin. (1) Only transmission (using the RXD pin as an I/O port) (2) Transmission and reception Port SCLK TXD 3800 group CS CLK DATA Peripheral IC (OSD controller etc.) Port SCLK TXD RXD 3800 group CS CLK IN OUT Peripheral IC (E2 PROM etc.) (3) Transmission and reception (Pins RXD and TXD are connected) (Pins IN and OUT in peripheral IC are connected) Port SCLK TXD RXD CS CLK IN OUT (4) Connecting ICs Port SCLK TXD RXD Port 3800 group CS CLK IN OUT Peripheral IC 1 3800 group T1 Peripheral IC T2 2 (E PROM etc.) T1: Select an N-channel open-drain output control of TXD pin. 2: Use such OUT pin of peripheral IC as an N-channel opendrain output in high impedance during receiving data. Note: "Port" is an output port controlled by software. CS CLK IN OUT Peripheral IC 2 Fig. 2.3.10 Serial I/O connection examples (1) 2-28 3800 GROUP USER'S MANUAL APPLICATION 2.3 Serial I/O (2) Connection with microcomputer Figure 2.3.11 shows connection examples of the other microcomputers. (1) Selecting an internal clock (2) Selecting an external clock SCLK TXD RXD 3800 group CLK IN OUT Microcomputer SCLK TXD RXD 3800 group CLK IN OUT Microcomputer (3) Using the SRDY siganl output function (Selecting an external clock) (4) Using UART SRDY RDY CLK IN OUT Microcomputer 3800 group Microcomputer TXD RXD RXD TXD SCLK TXD RXD 3800 group Fig. 2.3.11 Serial I/O connection examples (2) 3800 GROUP USER'S MANUAL 2-29 APPLICATION 2.3 Serial I/O 2.3.4 Setting of serial I/O transfer data format A clock synchronous or clock asynchronous (UART) is selected as a data format of the serial I/O. Figure 2.3.12 shows a setting of serial I/O transfer data format. 1ST-8DATA-1SP ST LSB MSB SP 1ST-7DATA-1SP ST LSB MSB SP 1ST-8DATA-1PAR-1SP ST LSB MSB PAR SP 1ST-7DATA-1PAR-1SP ST LSB MSB PAR SP UART 1ST-8DATA-2SP ST LSB MSB 2SP 1ST-7DATA-2SP ST LSB MSB 2SP Serial I/O 1ST-8DATA-1PAR-2SP ST LSB MSB PAR 2SP 1ST-7DATA-1PAR-2SP ST LSB MSB PAR 2SP Clock synchronous Serial I/O LSB first ST : Start bit SP : Stop bit PAR : Parity bit Fig. 2.3.12 Setting of Serial I/O transfer data format 2-30 3800 GROUP USER'S MANUAL APPLICATION 2.3 Serial I/O 2.3.5 Serial I/O application examples (1) Communication using a clock synchronous serial I/O (transmit/receive) Outline : 2-byte data is transmitted and received through the clock synchronous serial I/O. The signal is used for communication control. Figure 2.3.13 shows a connection diagram, and Figure 2.3.14 shows a timing chart. SRDY Transmitting side Receiving side P42/INT0 SRDY SCLK1 TXD 3800 group SCLK RXD 3800 group Fig. 2.3.13 Connection diagram [Communication using a clock synchronous serial I/O] Specifications : * * * * The Serial I/O is used (clock synchronous serial I/O is selected) Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32) The SRDY (receivable signal) is used. The receiving side outputs the SRDY signal at intervals of 2 ms (generated by timer), and 2-byte data is transferred from the transmitting side to the receiving side. SRDY **** SCLK TXD **** D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 **** 2 ms Fig. 2.3.14 Timing chart [Communication using a clock synchronous serial I/O] 3800 GROUP USER'S MANUAL 2-31 APPLICATION 2.3 Serial I/O Transmitting side Serial I/O status register (Address : 1916) b7 b0 SIOSTS Transmit buffer empty flag * Check to be transferred data from the Transmit buffer register to Transmit shift register. * Writable the next transmission data to the Transmit buffer register at being set to "1." Transmit shift register shift completion flag Check a completion of transmitting 1-byte data with this flag "1" : Transmit shift completed Serial I/O control register (Address : 1A16) b7 b0 SIOCON 1101 00 BRG counter source selection bit : f(XIN) Serial I/O synchronous clock selection bit : BRG/4 Transmit enable bit : Transmit enabled Receive enable bit : Receive disabled Serial I/O mode selection bit : Clock synchronous serial I/O Serial I/O enable bit : Serial I/O enabled Baud rate generator (Address : 1C16) b7 b0 BRG 7 Set "division ratio - 1" Interrupt edge selection register (Address : 3A16) b7 b0 INTEDGE 0 INT0 active edge selection bit : Select INT0 falling edge Fig. 2.3.15 Setting of related registers at a transmitting side [Communication using a clock synchronous serial I/O] 2-32 3800 GROUP USER'S MANUAL APPLICATION 2.3 Serial I/O Receiving side Serial I/O status register (Address : 1916) b7 b0 SIOSTS Receive buffer full flag Check a completion of receiving 1-byte data with this flag. "1" : At completing to receive "0" : At reading out a receive buffer Serial I/O control register (Address : 1A16) b7 b0 SIOCON 1111 11 Serial I/O synchronous clock selection bit : External clock SRDY output enable bit : Use the SRDY output Transmit enable bit : Transmit enabled Set this bit to "1," using SRDY output. Receive enable bit : Receive enabled Serial I/O mode selection bit : Clock synchronous serial I/O Serial I/O enable bit : Serial I/O enabled Fig. 2.3.16 Setting of related registers at a receiving side [Communication using a clock synchronous serial I/O] 3800 GROUP USER'S MANUAL 2-33 APPLICATION 2.3 Serial I/O Control procedure : Figure 2.3.17 shows a control procedure at a transmitting side, and Figure 2.3.18 shows a control procedure at a receiving side. RESET qX : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded. Initialization SIOCON (Address : 1A16) 1101XX002 8-1 (Address : 1C16) BRG INTEDGE (Address : 3A16), bit0 0 TB/RB (Address : 1816) TB/RB (Address : 1816) Fig. 2.3.17 Control procedure at a transmitting side [Communication using a clock synchronous serial I/O] ..... IREQ1 (Address : 3C16), bit0? 1 0 q Detect INT0 falling edge IREQ1 (Address : 3C16), bit0 0 The first byte of a transmission data q Write a transmission data The Transmit buffer empty flag is set to "0" by this writing. SIOSTS (Address : 1916), bit0? 1 The second byte of a transmission data 0 q Check to be transfered data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag) Write a transmission data The Transmit buffer empty flag is set to "0" by this writing. q SIOSTS (Address : 1916), bit0? 1 0 q Check to be transfered data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag) SIOSTS (Address : 1916), bit2? 1 0 q Check a shift completion of the Transmit shift register (Transmit shift register shift completion flag) 2-34 3800 GROUP USER'S MANUAL APPLICATION 2.3 Serial I/O RESET q X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded. Initialization SIOCON (Address : 1A16 ) ..... 1111X11X2 Pass 2 ms? Y TB/RB (Address : 1816 ) Dummy data N q An interval of 2 ms is generated by a timer. q SRDY output SRDY signal is output by writing data to the TB/RB. Using the SRDY , the transmit enabled bit (bit4) of the SIOCON is set to "1." SIOSTS (Address : 1916 ), bit1? 1 0 q Check a completion of receiving (Receive buffer full flag) Read out reception data from TB/RB (Address : 1816 ) q Receive the first byte data. A Receive buffer full flag is set to "0" by reading data. SIOSTS (Address : 1916 ), bit1? 1 0 q Check a completion of receiving (Receive buffer full flag) Read out reception data from TB/RB (Address : 1816 ) q Receive the second byte data. A Receive buffer full flag is set to "0" by reading data. Fig. 2.3.18 Control procedure at a receiving side [Communication using a clock synchronous serial I/O] 3800 GROUP USER'S MANUAL 2-35 APPLICATION 2.3 Serial I/O (2) Output of serial data (control of a peripheral IC) Outline : 4-byte data is transmitted and received through the clock synchronous serial I/O. The CS signal is output to a peripheral IC through the port P53. P53 SCLK TXD CS CLK DATA CS CLK DATA 3800 group Peripheral IC Fig. 2.3.19 Connection diagram [Output of serial data] Specifications : * * * * * The Serial I/O is used. (clock synchronous serial I/O is selected) Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32) Transfer direction : LSB first The Serial I/O1 interrupt is not used. The Port P53 is connected to the CS pin ("L" active) of the peripheral IC for a transmission control (the output level of the port P53 is controlled by software). Figre 2.3.20 shows an output timing chart of serial data. CS CLK DATA DO0 DO1 DO2 DO3 Fig. 2.3.20 Timing chart [Output of serial data] 2-36 3800 GROUP USER'S MANUAL APPLICATION 2.3 Serial I/O Figure 2.3.21 shows a setting of serial I/O related registers, and Figure 2.3.22 shows a setting of serial I/O transmission data. Serial I/O control register (Address : 1A16) b7 b0 SIOCON 11011000 BRG count source selection bit : f(XIN) Serial I/O synchronous clock selection bit : BRG/4 SRDY output enable bit : Not use the SRDY signal output function Transmit interrupt source selection bit : Transmit shift operating completion Transmit enable bit : Transmit enabled Receive enable bit : Receive disabled Serial I/O mode selection bit : Clock synchronous serial I/O Serial I/O enable bit : Serial I/O enabled UART control register (Address : 1B16) b7 b0 UARTCON 0 P45/TXD P-channel output disable bit : CMOS output Baud rate generator (Address : 1C16) b7 b0 BRG b7 7 Set "division ratio - 1" Interrupt control register 1 (Address : 3E16) b0 ICON1 0 Serial I/O transmit interrupt enable bit : Interrupt disabled Interrupt request register 1 (Address : 3C16) b7 b0 IREQ1 0 Serial I/O transmit interrupt request bit Using this bit, check the completion of transmitting 1-byte base data. "1" : Transmit shift completion Fig. 2.3.21 Setting of serial I/O related registers [Output of serial data] Transmit/Receive buffer register (Address : 18 16) b7 b0 TB/RB Set a transmission data. Check that transmission of the previous data is completed before writing data (bit 3 of the Interrupt request register 1 is set to "1"). Fig. 2.3.22 Setting of serial I/O transmission data [Output of serial data] 3800 GROUP USER'S MANUAL 2-37 APPLICATION 2.3 Serial I/O Control procedure : When the registers are set as shown in Figure 2.3.21, the Serial I/O can transmit 1-byte data simply by writing data to the Transmit buffer register. Thus, after setting the CS signal to "L," write the transmission data to the Receive buffer register on a 1-byte base, and return the CS signal to "H" when the desired number of bytes have been transmitted. Figure 2.3.23 shows a control procedure of serial I/O. RESET qX : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded. Initialization SIOCON (Address : 1A16) 110110002 UARTCON (Address : 1B16), bit4 0 (Address : 1C16) 8-1 BRG (Address : 3E16), bit3 ICON1 0 (Address : 0A16), bit3 P5 1 (Address : 0B16) P5D XXXX1XXX2 .... P5 (Address : 0A16 ), bit3 0 q TB/RB (Address : 1816 ) .... q Set the Serial I/O. Serial I/O transmit interrupt : Disabled Set the CS signal output port. ("H" level output) q q Set the CS signal output level to "L." IREQ1 (Address : 3C16 ), bit3 0 q Set the Serial I/O transmit interrupt request bit to "0." a transmission data q Write a transmission data. (start to transmit 1-byte data) IREQ1 (Address : 3C16 ), bit3? 1 0 q Check the completion of transmitting 1byte data. N q Complete to transmit data? q Y q Use any of RAM area as a counter for counting the number of transmitted bytes. Check that transmission of the target number of bytes has been completed. Return the CS signal output level to "H" when transmission of the target number of bytes is completed. P5 (Address : 0A16 ), bit3 1 Fig. 2.3.23 Control procedure of serial I/O [Output of serial data] 2-38 3800 GROUP USER'S MANUAL APPLICATION 2.3 Serial I/O (3) Cyclic transmission or reception of block data (data of a specified number of bytes) between microcomputers [without using an automatic transfer] Outline : When a clock synchronous serial I/O is used for communication, synchronization of the clock and the data between the transmitting and receiving sides may be lost because of noise included in the synchronizing clock. Thus, it is necessary to be corrected constantly. This "heading adjustment" is carried out by using the interval between blocks in this example. SCLK RXD TXD Master unit SCLK TXD RXD Slave unit Fig. 2.3.24 Connection diagram [Cyclic transmission or reception of block data between microcomputers] Specifications : * * * * * * * * The serial I/O is used (clock synchronous serial I/O is selected). Synchronous clock frequency : 131 kHz (f(XIN) = 4.19 MHz is divided by 32) Byte cycle: 488 s Number of bytes for transmission or reception : 8 byte/block Block transfer cycle : 16 ms Block transfer period : 3.5 ms Interval between blocks : 12.5 ms Heading adjustive time : 8 ms Limitations of the specifications 1. Reading of the reception data and setting of the next transmission data must be completed within the time obtained from "byte cycle - time for transferring 1-byte data" (in this example, the time taken from generating of the Serial I/O receive interrupt request to generating of the next synchronizing clock is 431 s). 2. "Heading adjustive time < interval between blocks" must be satisfied. 3800 GROUP USER'S MANUAL 2-39 APPLICATION 2.3 Serial I/O The communication is performed according to the timing shown below. In the slave unit, when a synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is processed as the beginning (heading) of a block. When a clock is input again after one block (8 byte) is received, the clock is ignored. Figure 2.3.26 shows a setting of related registers. D0 D1 D2 D7 D0 Byte cycle Block transfer period Block transfer cycle Heading adjustive time Interval between blocks Processing for heading adjustment Fig. 2.3.25 Timing chart [Cyclic transmission or reception of block data between microcomputers] Master unit Serial I/O control register (Address : 1A6) b7 b0 SIOCON Slave unit Serial I/O control register (Address : 1A16) b7 b0 SIOCON 1 1 1 1 BRG count source : f(XIN) Synchronous clock : BRG/4 Not use the SRDY output Transmit interrupt source : Transmit shift operating completion Transmit enabled Receive enabled Clock synchronous serial I/O Serial I/O enabled 11111000 01 Not be effected by external clock Synchronous clock : External clock Not use the SRDY output Not use the serial I/O transmit interrupt Transmit enabled Receive enabled Clock synchronous serial I/O Serial I/O enabled Both of units UART control register (Address : 1B16) b7 b0 UARTCON 0 P45/TXD pin : CMOS output Baud rate generator (Address : 1C16) b7 b0 BRG 7 Set "division ratio - 1" Fig. 2.3.26 Setting of related registers [Cyclic transmission or reception of block data between microcomputers] 2-40 3800 GROUP USER'S MANUAL APPLICATION 2.3 Serial I/O Control procedure : Control in the master unit After a setting of the related registers is completed as shown in Figure 2.3.33, in the master unit transmission or reception of 1-byte data is started simply by writing transmission data to the Transmit buffer register. To perform the communication in the timing shown in Figure 2.3.25, therefore, take the timing into account and write transmission data. Read out the reception data when the Serial I/O transmit interrupt request bit is set to "1," or before the next transmission data is written to the Transmit buffer register. A processing example in the master unit using timer interrupts is shown below. Interrupt processing routine executed every 488 s Note 1: When using the Index X mode flag (T). Note 2: When using the Decimal mode flag (D). Push the register used in the interrupt processing routine into the stack. CLT (Note 1) CLD (Note 2) Push register to stack q Within a block transfer period? Y Read a reception data N q Generate a certain block interval by using a timer or other functions. q Count a block interval counter Check the block interval counter and determine to start of a block transfer. Complete to transfer a block? N Write a transmission data Y Start a block transfer? Y Write the first transmission data (first byte) in a block N Pop registers q Pop registers which is pushed to stack. RTI Fig. 2.3.27 Control in the master unit 3800 GROUP USER'S MANUAL 2-41 APPLICATION 2.3 Serial I/O Control in the slave unit After a setting of the related registers is completed as shown in Figure 2.3.26, the slave unit becomes the state which is received a synchronizing clock at all times, and the Serial I/O receive interrupt request bit is set to "1" every time an 8-bit synchronous clock is received. By the serial I/O receive interrupt processing routine, the data to be transmitted next is written to the Transmit buffer register after received data is read out. However, if no serial I/O receive interrupt occurs for more than a certain time (head adjustive time), the following processing will be performed. 1. The first 1 byte data of the transmission data in the block is written into the Transmit buffer register. 2. The data to be received next is processed as the first 1 byte of the received data in the block. Figure 2.3.28 shows the control in the slave unit using a serial I/O receive interrupt and any timer interrupt (for head adjustive). Serial I/O receive interrupt processing routine Timer interrupt processing routine CLT (Note 1) CLD (Note 2) Push register to stack q Push the register used in the interrupt processing routine into the stack. Check the received byte counter to judge if a block has been transfered. CLT (Note 1) CLD (Note 2) Push register to stack q Push the register used in the interrupt processing routine into the stack. q Within a block transfer period? Y Read a reception data N Heading adjustive counter - 1 Heading adjustive counter = 0? Y N A received byte counter +1 Write the first transmission data (first byte) in a block A received byte counter 8? N Y A received byte counter 0 Pop registers Write a transmission data Write any data (FF16) RTI Heading adjustive counter Initialized value (Note 3) q Pop registers which is pushed to stack. Pop registers q Pop registers which is pushed to stack. Notes 1: When using the Index X mode flag (T). 2: When using the Decimal mode flag (D). 3: In this example, set the value which is equal to the heading adjustive time divided by the timer interrupt cycle as the initialized value of the heading adjustive counter. For example: When the heading adjustive time is 8 ms and the timer interrupt cycle is 1 ms, set 8 as the initialized value. RTI Fig. 2.3.28 Control in the slave unit 2-42 3800 GROUP USER'S MANUAL APPLICATION 2.3 Serial I/O (4) Communication (transmit/receive) using an asynchronous serial I/O (UART) Point : 2-byte data is transmitted and received through an asynchronous serial I/O. The port P40 is used for communication control. Figure 2.3.29 shows a connection diagram, and Figure 2.3.30 shows a timing chart. Transmitting side P40 Receiving side P40 TXD R XD 3800 group 3800 group Fig. 2.3.29 Connection diagram [Communication using UART] Specifications : * The Serial I/O is used (UART is selected). * Transfer bit rate : 9600 bps (f(XIN) = 4.9152 MHz is divided by 512) * Communication control using port P40 (The output level of the port P40 is controlled by softoware.) * 2-byte data is transferred from the transmitting side to the receiving side at intervals of 10 ms (generated by timer). P40 TXD ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 10 ms Fig. 2.3.30 Timing chart [Communication using UART] 3800 GROUP USER'S MANUAL 2-43 APPLICATION 2.3 Serial I/O Table 2.3.1 shows setting examples of Baud rate generator (BRG) values and transfer bit rate values, Figure 2.3.31 shows a setting of related registers at a transmitting side, and Figure 2.3.32 shows a setting of related registers at a receiving side. Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values Transfer bit BRG count at f(XIN) = 4.9152 MHZ at f(XIN) = 7.3728 MHZ at f(XIN) = 8 MHZ rate (bps) source (Note 1) (Note 2) BRG setting value Actual time (bps) BRG setting value Actual time (bps) BRG setting value Actual time (bps) 600 1200 2400 4800 9600 19200 38400 76800 31250 62500 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN) f(XIN) f(XIN) 127(7F16) 63(3F16) 31(1F16) 15(0F16) 7(0716) 3(0316) 1(0116) 3(0316) 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 76800.00 191(BF16) 95(5F16) 47(2F16) 23(1716) 11(0B16) 5(0516) 2(0216) 5(0516) 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 76800.00 207(CF16) 103(6716) 51(3316) 25(1916) 12(0C16) 5(0516) 2(0216) 5(0516) 15(0F16) 7(0716) 600.96 1201.92 2403.85 4807.69 9615.38 20833.33 41666.67 83333.33 31250.00 62500.00 Notes 1: Equation of transfer bit rate Transfer bit rate (bps) = f(XIN) (BRG setting value + 1) ! 16 ! m m: when bit 0 of the Serial I/O control register (Address : 1A16) is set to "0," a value of m is 1. when bit 0 of the Serial I/O control register (Address : 1A16) is set to "1," a value of m is 4. 2: A BRG count source is selected by bit 0 of the Serial I/O control register (Address : 1A16). 2-44 3800 GROUP USER'S MANUAL APPLICATION 2.3 Serial I/O Transmitting side Serial I/O status register (Address : 1916) b7 b0 SIOSTS Transmit buffer empty flag * Check to be transferred data from the Transmit buffer register to the Transmit shift register. * Writable the next transmission data to the Transmit buffer register at being set to "1." Transmit shift register shift completion flag Check a completion of transmitting 1-byte data with this flag. "1" : Transmit shift completed Serial I/O control register (Address : 1A16) b7 b0 SIOCON 1001 001 BRG count source selection bit : f(XIN)/4 Serial I/O synchronous clock selection bit : BRG/16 SRDY output enable bit : Not use SRDY out Transmit enable bit : Transmit enabled Receive enable bit : Receive disabled Serial I/O mode selection bit : Asynchronous serial I/O(UART) Serial I/O enable bit : Serial I/O enabled UART control register (Address : 1B16) b7 b0 UARTCON 01 00 Character length selection bit : 8 bits Parity enable bit : Parity checking disabled Stop bit length selection bit : 2 stop bits P45/TXD P-channel output disable bit : CMOS output Baud rate generator (Address : 1C16) b7 b0 f(XIN) Set Transfer bit rate ! 16 ! m T BRG 7 -1 T when bit 0 of the Serial I/O control register (Address : 1A16) is set to "0," a value of m is 1. when bit 0 of the Serial I/O control register (Address : 1A16) is set to "1," a value of m is 4. Fig. 2.3.31 Setting of related registers at a transmitting side [Communication using UART] 3800 GROUP USER'S MANUAL 2-45 APPLICATION 2.3 Serial I/O Receiving side Serial I/O status register (Address : 1916) b7 b0 SIOSTS Receive buffer full flag Check a completion of receiving 1-byte data with this flag. "1" : at completing to receive "0" : at reading out a content of the Receive buffer register Overrun error flag "1" : when data are ready to be transferred to the Receive shift register in the state of storing data into the Receive buffer register. Parity error flag "1" : when parity error occurs at enabled parity. Framing error flag "1" : when data can not be received at the timing of setting a stop bit. Summing error flag "1" : when even one of the following errors occurs. * Overrun error * Parity error * Framing error Serial I/O control register (Address : 1A16) b7 b0 SIOCON 1 0 1 0 001 BRG count source selection bit : f(XIN)/4 Serial I/O synchronous clock selection bit : BRG/16 SRDY output enable bit : Not use SRDY out Transmit enable bit : Transmit disabled Receive enable bit : Receive enabled Serial I/O mode selection bit : Asynchronous serial I/O(UART) Serial I/O enable bit : Serial I/O enabled UART control register (Address : 1B16) b7 b0 UARTCON 1 00 Character length selection bit : 8 bits Parity enable bit : Parity checking disabled Stop bit length selection bit : 2 stop bits Baud rate generator (Address : 1C16) b7 b0 BRG 7 -1 Transfer bit rate ! 16 ! m T T when bit 0 of the Serial I/O control register (Address : 1A16) is set to "0," a value of m is 1. when bit 0 of the Serial I/O control register (Address : 1A16) is set to "1," a value of m is 4. Set f(XIN) Fig. 2.3.32 Setting of related registers at a receiving side [Communication using UART] 2-46 3800 GROUP USER'S MANUAL APPLICATION 2.3 Serial I/O Control procedure : Figure 2.3.33 shows a control procedure at a transmitting side, and Figure 2.3.34 shows a control procedure at a receiving side. RESET qX : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded. Initialization SIOCON UARTCON BRG P4 P4D .... (Address : 1A16) 1001X0012 (Address : 1B16) 000010002 (Address : 1C16) 8-1 (Address : 0816), bit0 0 XXXXXXX12 (Address : 0916) q Set port P40 for a communication control. Pass 10 ms? Y P4 (Address : 0816), bit0 1 N q An interval of 10 ms is generated by a timer. q Start of communication. Write a transmission data The Transmit buffer empty flag is set to "0" by this writing. Check to be transferred data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag) TB/RB (Address : 1816) The first byte of a transmission data q SIOSTS (Address : 1916), bit0? 1 The second byte of a transmission data 0 q q TB/RB (( ddress : 1816) A Write a transmission data The Transmit buffer empty flag is set to "0" by this writing. Check to be transferred data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag) SIOSTS (Address : 1916), bit0? 1 0 q SIOSTS (Address : 1916), bit2? 1 P4 (Address : 0816), bit0 0 0 q Check a shift completion of the Transmit shift register. (Transmit shift register shift completion flag) q End of communication Fig. 2.3.33 Control procedure at a transmitting side [Communication using UART] 3800 GROUP USER'S MANUAL 2-47 APPLICATION 2.3 Serial I/O RESET qX : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded. Initialization SIOCON (Address : 1A16) UARTCON (Address : 1B16) (Address : 1C16) BRG (Address : 0916) P4D .... 1010X0012 000010002 8 --1 XXXXXXX02 SIOSTS (Address : 1916 ), bit1? 1 q 0 q Check a completion of receiving. (Receive buffer full flag) Receive the first 1 byte data A Receive buffer full flag is set to "0" by reading data. Check an error falag. Read out a reception data from RB (Address : 1816) q SIOSTS (Address : 1916 ), bit6? 0 1 SIOSTS (Address : 1916 ), bit1? 1 0 q Check a completion of receiving. (Receive buffer full flag) q Read out a reception data from RB (Address : 1816 ) Receive the second byte data A Receive buffer full flag is set to "0" by reading data. Check an error flag. Processing for error SIOSTS (Address : 1916 ), bit6? 0 1 q 1 P4 (Address : 0816 ), bit0? 0 SIOCON (Address : 1A16 ) SIOCON (Address : 1A16 ) 0000X0012 1010X0012 * Countermeasure for a bit slippage Fig. 2.3.34 Control procedure at a receiving side [Communication using UART] 2-48 3800 GROUP USER'S MANUAL APPLICATION 2.4 Processor mode 2.4 Processor mode 2.4.1 Memory map of processor mode 003B16 CPU mode register (CPUM) Fig. 2.4.1 Memory map of processor mode related register 2.4.2 Related register CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Adress : 3B16 ] B Name 0 Processor mode bits 1 2 Stack page selection bit Function 00 : Single-chip mode 01 : Memory expansion mode 10 : Microprocessor mode 11 : Not available 0 : 0 page 1 : 1 page At reset RW 0 T 0 0 0 0 0 0 ! ! ! ! ! ! 3 Nothing is allocated for these bits. These are write 4 disabled bits. When these bits are read out, the 5 values are "0." 6 7 T An initial value of bit 1 is determined by a level of the CNVSS pin. Fig. 2.4.2 Structure of CPU mode register 3800 GROUP USER'S MANUAL 2-49 APPLICATION 2.4 Processor mode 2.4.3 Processor mode application examples (1) Application example of memory expansion in the case where the ONW (One-Wait) function is not used Outline : The external memory is accessed in the microprocessor mode. At f(XIN) = 8 MHz, an available RAM is given by the following : * OE access time : ta (OE) 50 ns * Setup time for writing data : tsu (D) 65 ns For example, the M5M5256BP-10 whose address access is 100 ns is available. Figure 2.4.3 shows an expansion example of a 32K byte ROM and a 32K byte RAM. 3800 group CNVSS AD15 ONW M5M27C256AK-10 2 P30 , P31 AD14 8 P4 15 M5M5256BP-10 S CE 74F04 A0-A14 EPROM - AD0 A0-A14 SRAM 8 P5 DB0 DB7 - 8 D0-D7 OE DQ1-DQ8 OE W 8 P6 RD Memory map 000016 External RAM area (M5M5256BP) 000816 2 P7 WR SFR area 004016 Internal RAM area 044016 External RAM area (M5M5256BP) 8MHz VCC = 5.0V 10 % 800016 External ROM area (M5M27C256AK) FFFF16 Fig. 2.4.3 Expansion example of ROM and RAM 2-50 3800 GROUP USER'S MANUAL APPLICATION 2.4 Processor mode Figure 2.4.4, Figure 2.4.5 and Figure 2.4.6 show a standard timing at 8 MHz (No-Wait). A0-A7 (Port P0) Address (low-order) A8-A14 (Port P1) Address (high-order) S (A15) OE (RD of 3800) td(AH--RD) 125 ns - 35 ns (min) tWL(RD) 125 ns - 10 ns (min) ta(OE) 50 ns (max) DQ1-DQ8 (Port P2) Data tsu(DB--RD) 65 ns (min) "H" level WR td(AH--RD) tWL(RD) ta(OE) tsu(DB--RD) : RD delay time after outputting address of 3800 : RD pulse width of 3800 : Output enabled access time of M5M5256BP : Data bus setup time before RD of 3800 Fig. 2.4.4 Read-cycle (OE access, SRAM) A0-A7 (Port P0) Address (low-order) A8-A14 (Port P1) Address (high-order) CE 5.8 ns (max) tPHL OE (RD of 3800) td(AH--RD) 125 ns - 35 ns (min) tWL(RD) 125 ns - 10ns (min) ta(OE) 50 ns (max) D0-D7 (Port P2) Data tsu(DB--RD) 65 ns (min) WR "H" level tPHL td(AH--RD) tWL(RD) ta(OE) tsu(DB--RD) : : : : : Output delay time of 74F04 RD delay time after outputting address of 3800 RD pulse width of 3800 Output enabled access time of M5M27C256AK Data bus setup time before RD of 3800 Fig. 2.4.5 Read-cycle (OE access, EPROM) 3800 GROUP USER'S MANUAL 2-51 APPLICATION 2.4 Processor mode A0-A7 (Port P0) Address (low-order) A8-A14 (Port P1) Address (high-order) S (A15) W (WR of 3800) td(AH--WR) 125 ns - 35 ns (min) tWL(WR) 125 ns - 10 ns (min) td(WR--DB) DQ1-DQ8 (Port P2) 65 ns (max) Data tsu(D) 35 ns (min) OE (RD of 3800) " H " level td(AH--WR) tWL(WR) td(WR--DB) tsu(D) : : : : WR delay time after outputting address of 3800 WR pulse width of 3800 Data bus delay time after WR of 3800 Data setup time of M5M5256BP Fig. 2.4.6 Write-cycle (W control, SRAM) 2-52 3800 GROUP USER'S MANUAL APPLICATION 2.4 Processor mode (2) Application example of memory expansion in the case where the ONW (One-Wait) function is used Outline : ONW function is used when the external memory access is slow. If "L" level signal is input to the P32/ONW pin while the CPU is in the read or write status, the read or write cycle corresponding to 1 cycle of is extended. In the extended period, the RD or WR signal is kept at the "L" level. The ONW function operates only when data is read from or written into addresses 000016 to 000716 and addresses 044016 to FFFF16. Figure 2.4.7 shows an application example of the ONW function. 3800 group CNVSS AD15 2 P30, P31 ONW 8 P4 AD14 15 74F04 M5M27C256AK-10 CE M5M5256BP-10 S A0-A14 SRAM AD0 EPROM 8 P5 DB0 DB7 8 P6 RD WR 2 P7 8MHz VCC= 5.0V 10 % 000816 - 8 Fig. 2.4.7 Application example of the ONW function - A0-A14 D0-D7 OE DQ1-DQ8 OE W Memory map 000016 External RAM area (M5M5256BP) SFR area 004016 Internal RAM area 044016 External RAM area (M5M5256BP) 800016 External ROM area FFFF16 (M5M27C256AK) ____ 3800 GROUP USER'S MANUAL 2-53 APPLICATION 2.5 Reset 2.5 Reset 2.5.1 Connection example of reset IC 91 1 VCC Power source M62022L GND 3 5 Output 35 RESET Delay capacity 4 0.1 F 40 VSS 3800 group Fig. 2.5.1 Example of Poweron reset circuit Figure 2.5.2 shows the system example which switch to the RAM backup mode by detecting a drop of the system power source voltage with the INT interrupt. System power source voltage +5 91 + 7 VCC VCC1 RESET 2 5 35 RESET VCC2 INT 3 40 INT VSS 1 V1 GND Cd 4 6 3800 group M62009L, M62009P, M62009FP Fig. 2.5.2 RAM back-up system 2-54 3800 GROUP USER'S MANUAL CHAPTER 3 APPENDIX 3.1 Electrical characteristics 3.2 Standard characteristics 3.3 Notes on use 3.4 Countermeasures against noise 3.5 List of registers 3.6 Mask ROM ordering method 3.7 Mark specification form 3.8 Package outline 3.9 List of instruction codes 3.10 Machine instructions 3.11 SFR memory map 3.12 Pin configuration APPENDIX 3.1 Electrical characteristics 3.1 Electrical characteristics 3.1.1 Absolute maximum ratings Table 3.1.1 Absolute maximum ratings Parameter Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 VI Input voltage RESET, XIN VI Input voltage CNVSS VO Output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71, XOUT Pd Power dissipation Topr Operating temperature Tstg Storage temperature Note : 300 mW in case of the flat package. Symbol VCC VI Conditions Ratings -0.3 to 7.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to 13 -0.3 to VCC +0.3 Ta = 25 C 1000(Note) -20 to 85 -40 to 125 Unit V V V V V mW C C All voltages are based on VSS. Output transistors are cut off. 3.1.2 Recommended operating conditions Table 3.1.2 Recommended operating conditions (VCC = 3.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC VSS VIH VIH VIL VIL VIL IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(XIN) Power source voltage (Note 1) Power source voltage "H" input voltage Parameter (f(XIN) 2 MHz) (f(XIN) = 8 MHz) Limits Min. 3.0 4.0 Typ. 5.0 5.0 0 Max. 5.5 5.5 Unit V V VCC VCC 0.2 VCC 0.2 VCC 0.16 VCC -80 -80 80 80 -40 -40 40 40 -10 10 -5 5 V V V V V mA mA mA mA mA mA mA mA mA mA mA mA P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 "H" input voltage RESET, XIN, CNVSS "L" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 "L" input voltage RESET, CNVSS "L" input voltage XIN "H" total peak output current P00-P07, P10-P17, P20-P27, P30-P37(Note 2) "H" total peak output current P40-P47,P50-P57, P60-P67, P70, P71(Note 2) "L" total peak output current P00-P07, P10-P17, P20-P27, P30-P37(Note 2) "L" total peak output current P40-P47,P50-P57, P60-P67, P70, P71(Note 2) "H" total average output current P00-P07, P10-P17, P20-P27, P30-P37(Note 2) "H" total average output current P40-P47,P50-P57, P60-P67, P70, P71(Note 2) "L" total average output current P00-P07, P10-P17, P20-P27, P30-P37(Note 2) "L" total average output current P40-P47,P50-P57, P60-P67, P70, P71(Note 2) "H" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71(Note 3) "L" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71(Note 3) "H" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71(Note 4) "L" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71(Note 4) Internal clock oscillation frequency (4.0 VVcc5.5 V) Internal clock oscillation frequency (3.0 VVcc4.0 V) 0.8 VCC 0.8 VCC 0 0 0 8 MHz 6 VCC-16 Note 1: The minimum power source voltage is X + 16 [V] (f(XIN) = XMHz) on the condition of 2 MHz < f(XIN) < 8 MHz. 6 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 3: The peak output current is the peak current flowing in each port. 4: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms. 3-2 3800 GROUP USER'S MANUAL APPENDIX 3.1 Electrical characteristics 3.1.3 Electrical characteristics Table 3.1.3 Electrical characteristics (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter "H" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 (Note) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,P50-P57, P60-P67, P70, P71 Hysteresis Hysteresis Hysteresis "H" input current CNTR0, CNTR1, INT0-INT5 RXD, SCLK RESET P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 RESET, CNVSS XIN P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 RESET, CNVSS XIN Test conditions IOH = -10 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 3.0 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 3.0 to 5.5 V Limits Min. VCC-2.0 V VCC-1.0 2.0 V 1.0 0.4 0.5 0.5 VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS When clock stopped f(XIN) = 8 MHz, VCC = 5 V f(XIN) = 5 MHz, VCC = 5 V f(XIN) = 2 MHz, VCC = 3 V When WIT instruction is executed with f(XIN) = 8 MHz, VCC = 5 V When WIT instruction is executed with f(XIN) = 5 MHz, VCC = 5 V When WIT instruction is executed with f(XIN) = 2 MHz, VCC = 3 V When STP instruction Ta = 25 C is executed with clock stopped, output Ta = 85 C transistors isolated. -4 2.0 6.4 4 0.8 1.5 1 0.2 0.1 1 A 10 5.5 13 8 2.0 5.0 5.0 4 -5.0 V V V A A A A A V Typ. Max. Unit VOH VOL VT+ - VT- VT+ - VT- VT+ - VT- IIH IIH IIH IIL "H" input current "H" input current "L" input current IIL VRAM "L" input current RAM hold voltage mA ICC Power source current Note : P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 3800 GROUP USER'S MANUAL 3-3 APPENDIX 3.1 Electrical characteristics 3.1.4 Timing requirements and Switching characteristics Table 3.1.4 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tc(XIN) tWH(XIN) tWL(XIN) tc(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tc(SCLK) tWH(SCLK) tWL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT5 input "H" pulse width INT0 to INT5 input "L" pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input "H" pulse width (Note) Serial I/O clock input "L" pulse width (Note) Serial I/O input set up time Serial I/O input hold time Min. 2 125 50 50 200 80 80 80 80 800 370 370 220 100 Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns Note: When bit 6 of address 001A16 is "1". Divide this value by four when bit 6 of address 001A16 is "0". Table 3.1.5 Timing requirements (2) (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tc(XIN) tWH(XIN) tWL(XIN) tc(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tc(SCLK) tWH(SCLK) tWL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT5 input "H" pulse width INT0 to INT5 input "L" pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input "H" pulse width (Note) Serial I/O clock input "L" pulse width (Note) Serial I/O input set up time Serial I/O input hold time Parameter Min. 2 500/ (3 VCC-8) 200/ (3 VCC-8) 200/ (3 VCC-8) 500 230 230 230 230 2000 950 950 400 200 Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns Note: When bit 6 of address 001A16 is "1" (clock synchronous mode). Divide this value by four when bit 6 of address 001A16 is "0" (UART mode). 3-4 3800 GROUP USER'S MANUAL APPENDIX 3.1 Electrical characteristics Table 3.1.6 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-TXD) tv(SCLK-TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Test conditions Min. tc(SCLK)/2-30 tc(SCLK)/2-30 -30 30 30 30 30 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns 140 Fig. 3.1.1 10 10 Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: XOUT pin is excluded. Table 3.1.7 Switching characteristics (2) (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-TXD) tv(SCLK-TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Test conditions Min. tc(SCLK)/2-50 tc(SCLK)/2-50 -30 50 50 50 50 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns 350 Fig. 3.1.1 20 20 Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: XOUT pin is excluded. 3800 GROUP USER'S MANUAL 3-5 APPENDIX 3.1 Electrical characteristics Table 3.1.8 Timing requirements in memory expansion mode and microprocessor mode (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Parameter Before ONW input set up time After ONW input hold time Before data bus set up time After data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time Limits Min. -20 -20 60 0 -20 -20 65 0 Typ. Max. Unit ns ns ns ns ns ns ns ns Symbol tsu(ONW-) th(-ONW) tsu(DB-) th(-DB) tsu(ONW-RD) tsu(ONW-WR) th(RD-ONW) th(WR-ONW) tsu(DB-RD) th(RD-DB) Table 3.1.9 Switching characteristics in memory expansion mode and microprocessor mode (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Parameter Test conditions Limits Min. tc(XIN)-10 tc(XIN)-10 6 6 20 10 25 10 20 10 10 5 20 40 45 Typ. 2tc(XIN) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tc(XIN)-15 tc(XIN)-20 5 5 15 10 0 200 200 65 ns ns ns ns ns ns ns ns Symbol tc() clock cycle time clock "H" pulse width clock "L" pulse width After AD15-AD8 delay time After AD15-AD8 valid time After AD7-AD0 delay time After AD7-AD0 valid time SYNC delay time tv(-SYNC) SYNC valid time td(-WR) RD and WR delay time tv(-WR) RD and WR valid time td(-DB) After data bus delay time tv(-DB) After data bus valid time RD pulse width, WR pulse width twL(RD) RD pulse width, WR pulse width twL(WR) (When one-wait is valid) td(AH-RD) After AD15-AD8 RD delay time td(AH-WR) After AD15-AD8 WR delay time td(AL-RD) After AD7-AD0 RD delay time td(AL-WR) After AD7-AD0 WR delay time tv(RD-AH) After RD AD15-AD8 valid time tv(WR-AH) After WR AD15-AD8 valid time tv(RD-AL) After RD AD7-AD0 valid time tv(WR-AL) After WR AD7-AD0 valid time td(WR-DB) After WR data bus delay time tv(WR-DB) After WR data bus valid time td(RESET-RESETOUT) RESETOUT output delay time tv(-RESET) RESETOUT output valid time (Note) twH() twL() td(-AH) tv(-AH) td(-AL) tv(-AL) td(-SYNC) 3 15 tc(XIN)-10 3tc(XIN)-10 tc(XIN)-35 tc(XIN)-40 0 0 20 10 70 Fig. 3.1.1 Note : The RESETOUT goes "H" in sync with the fall of the clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes "H". 3-6 3800 GROUP USER'S MANUAL APPENDIX 3.1 Electrical characteristics Table 3.1.10 Timing requirements in memory expansion mode and microprocessor mode (2) (VCC = 3.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tsu(ONW-) th(-ONW) tsu(DB-) th(-DB) tsu(ONW-RD) tsu(ONW-WR) th(RD-ONW) th(WR-ONW) tsu(DB-RD) th(RD-DB) Before ONW input set up time After ONW input hold time Before data bus set up time After data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time Parameter Limits Min. -20 -20 180 0 -20 -20 185 0 Typ. Max. Unit ns ns ns ns ns ns ns ns Table 3.1.11 Switching characteristics in memory expansion mode and microprocessor mode (2) (VCC = 3.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tc() twH() twL() td(-AH) tv(-AH) td(-AL) tv(-AL) td(-SYNC) tv(-SYNC) td(-WR) tv(-WR) td(-DB) tv(-DB) Parameter Test conditions Min. tc(XIN)-20 tc(XIN)-20 150 10 10 15 150 15 40 20 15 7 Limits Typ. 2tc(XIN) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 195 10 0 300 300 ns ns ns ns ns ns clock cycle time clock "H" pulse width clock "L" pulse width After AD15-AD8 delay time After AD15-AD8 valid time After AD7-AD0 delay time After AD7-AD0 valid time SYNC delay time SYNC valid time RD and WR delay time RD and WR valid time After data bus delay time After data bus valid time RD pulse width, WR pulse width twL(RD) RD pulse width, WR pulse width twL(WR) (When one-wait is valid) td(AH-RD) After AD15-AD8 RD delay time td(AH-WR) After AD15-AD8 WR delay time td(AL-RD) After AD7-AD0 RD delay time td(AL-WR) After AD7-AD0 WR delay time tv(RD-AH) After RD AD15-AD8 valid time tv(WR-AH) After WR AD15-AD8 valid time tv(RD-AL) After RD AD7-AD0 valid time tv(WR-AL) After WR AD7-AD0 valid time td(WR-DB) After WR data bus delay time tv(WR-DB) After WR data bus valid time td(RESET-RESETOUT) RESETOUT output delay time tv(-RESET) RESETOUT output valid time (Note) 3 15 tc(XIN)-20 3tc(XIN)-20 tc(XIN)-145 tc(XIN)-145 5 5 25 15 200 Fig. 3.1.1 Note: The RESETOUT goes "H" in sync with the fall of the clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes "H". 3800 GROUP USER'S MANUAL 3-7 APPENDIX 3.1 Electrical characteristics 3.1.5 Absolute maximum ratings (Extended operating temperature version) Table 3.1.12 Absolute maximum ratings (Extended operating temperature version) Symbol VCC VI Parameter Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 Input voltage RESET, XIN Input voltage CNVSS Output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71, XOUT Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 to 7.0 -0.3 to VCC +0.3 All voltages are based on VSS. Output transistors are cut off. -0.3 to VCC +0.3 -0.3 to 13 -0.3 to VCC +0.3 Ta = 25 C 1000(Note) -40 to 85 -65 to 150 Unit V V V V V mW C C VI VI VO Pd Topr Tstg Note : 300 mW in case of the flat package. 3.1.6 Recommended operating conditions (Extended operating temperature version) Table 3.1.13 Recommended operating conditions (Extended operating temperature version) (VCC = 4.0 to 5.5 V, Ta = -40 to 85 C, unless otherwise noted) Symbol VCC VSS VIH VIH VIL VIL VIL IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(XIN) Power source voltage Power source voltage "H" input voltage Parameter Min. 4.0 Limits Typ. 5.0 0 Max. 5.5 Unit V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 "H" input voltage RESET, XIN, CNVSS "L" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 "L" input voltage RESET, CNVSS "L" input voltage XIN "H" total peak output current P00-P07, P10-P17, P20-P27, P30-P37 (Note 1) "H" total peak output current P40-P47,P50-P57, P60-P67, P70, P71 (Note 1) "L" total peak output current P00-P07, P10-P17, P20-P27, P30-P37 (Note 1) "L" total peak output current P40-P47,P50-P57, P60-P67, P70, P71 (Note 1) "H" total average output current P00-P07, P10-P17, P20-P27, P30-P37 (Note 1) "H" total average output current P40-P47,P50-P57, P60-P67, P70, P71 (Note 1) "L" total average output current P00-P07, P10-P17, P20-P27, P30-P37 (Note 1) "L" total average output current P40-P47,P50-P57, P60-P67, P70, P71 (Note 1) "H" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 (Note 2) "L" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 (Note 2) "H" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 (Note 3) "L" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 (Note 3) Internal clock oscillation frequency 0.8 VCC 0.8 VCC 0 0 0 VCC VCC 0.2 VCC 0.2 VCC 0.16 VCC -80 -80 80 80 -40 -40 40 40 -10 10 -5 5 8 Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms. 3-8 3800 GROUP USER'S MANUAL APPENDIX 3.1 Electrical characteristics 3.1.7 Electrical characteristics (Extended operating temperature version) Table 3.1.14 Electrical characteristics (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol VOH Parameter "H" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 (Note) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,P50-P57, P60-P67, P70, P71 Hysteresis CNTR0, CNTR1, INT0-INT5 Hysteresis RXD, SCLK Hysteresis RESET "H" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71 "H" input current RESET, CNVSS "H" input current XIN "L" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70, P71, RESET, CNVSS "L" input current XIN RAM hold voltage Test conditions IOH = -10 mA Limits Min. VCC-2.0 Typ. Max. Unit V VOL VT+ - VT- VT+ - VT- VT+ - VT- IIH IIH IIH IIL IIL VRAM IOL = 10 mA 0.4 0.5 0.5 VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS When clock stopped f(XIN) = 8 MHz f(XIN) = 5 MHz When WIT instruction is executed with f(XIN) = 8 MHz When WIT instruction is executed with f(XIN) = 5 MHz When STP instruction is executed with clock Ta = 25 C stopped, output Ta = 85 C transistors isolated. -4 2.0 6.4 4 1.5 1 0.1 2.0 V V V V 5.0 5.0 4 -5.0 A A A A A V 5.5 13 8 mA ICC Power source current 1 A 10 Note : P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 3800 GROUP USER'S MANUAL 3-9 APPENDIX 3.1 Electrical characteristics 3.1.8 Timing requirements and Switching characteristics (Extended operating temperature version) Table 3.1.15 Timing requirements (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tW(RESET) tc(XIN) tWH(XIN) tWL(XIN) tc(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tc(SCLK) tWH(SCLK) tWL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT5 input "H" pulse width INT0 to INT5 input "L" pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input "H" pulse width (Note) Serial I/O clock input "L" pulse width (Note) Serial I/O input set up time Serial I/O input hold time Min. 2 125 50 50 200 80 80 80 80 800 370 370 220 100 Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns Note: Bit 6 of address 001A16 is "1". Divide this value by four bit 6 of address 001A16 is "0". Table 3.1.16 Switching characteristics (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-TXD) tv(SCLK-TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rise time Serial I/O clock output fall time CMOS output rise time (Note 2) CMOS output fall time (Note 2) Test conditions Min. tc(SCLK)/2-30 tc(SCLK)/2-30 -30 30 30 30 30 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns 140 Fig. 3.1.1 10 10 Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: XOUT pin is excluded. 3-10 3800 GROUP USER'S MANUAL APPENDIX 3.1 Electrical characteristics Table 3.1.17 Timing requirements in memory expansion mode and microprocessor mode (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tsu(ONW-) th(-ONW) tsu(DB-) th(-DB) tsu(ONW-RD) tsu(ONW-WR) th(RD-ONW) th(WR-ONW) tsu(DB-RD) th(RD-DB) Before ONW input set up time After ONW input hold time Before data bus set up time After data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time Parameter Limits Min. -20 -20 60 0 -20 -20 65 0 Typ. Max. Unit ns ns ns ns ns ns ns ns Table 3.1.18 Switching characteristics in memory expansion mode and microprocessor mode (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tc() twH() twL() td(-AH) tv(-AH) td(-AL) tv(-AL) td(-SYNC) tv(-SYNC) td(-WR) tv(-WR) td(-DB) tv(-DB) Parameter Test conditions Limits Min. tc(XIN)-10 tc(XIN)-10 6 6 20 10 25 10 20 10 10 5 20 40 45 Typ. 2tc(XIN) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tc(XIN)-15 tc(XIN)-20 5 5 15 10 0 200 200 65 ns ns ns ns ns ns ns ns clock cycle time clock "H" pulse width clock "L" pulse width After AD15-AD8 delay time After AD15-AD8 valid time After AD7-AD0 delay time After AD7-AD0 valid time SYNC delay time SYNC valid time RD and WR delay time RD and WR valid time After data bus delay time After data bus valid time RD pulse width, WR pulse width twL(RD) RD pulse width, WR pulse width twL(WR) (When one-wait is valid) td(AH-RD) After AD15-AD8 RD delay time td(AH-WR) After AD15-AD8 WR delay time td(AL-RD) After AD7-AD0 RD delay time td(AL-WR) After AD7-AD0 WR delay time tv(RD-AH) After RD AD15-AD8 valid time tv(WR-AH) After WR AD15-AD8 valid time tv(RD-AL) After RD AD7-AD0 valid time tv(WR-AL) After WR AD7-AD0 valid time td(WR-DB) After WR data bus delay time tv(WR-DB) After WR data bus valid time td(RESET-RESETOUT) RESETOUT output delay time tv(-RESET) RESETOUT output valid time (Note) 3 15 tc(XIN)-10 3tc(XIN)-10 tc(XIN)-35 tc(XIN)-40 0 0 20 10 70 Fig. 3.1.1 Note : The RESETOUT output goes "H" in sync with the fall of the clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes "H". Measurement output pin 100pF CMOS output Fig. 3.1.1 Circuit for measuring output switching characteristics 3800 GROUP USER'S MANUAL 3-11 APPENDIX 3.1 Electrical characteristics 3.1.9 Timing diagram Timing Diagram tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2 VCC CNTR0, CNTR1 0.8 VCC tWH(INT) tWL(INT) 0.2 VCC INT0-INT5 0.8 VCC tW(RESET) RESET 0.2 VCC 0.8 VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2 VCC XIN 0.8 VCC tf tWL(SCLK) 0.2 VCC tC(SCLK) tr 0.8 VCC tWH(SCLK) SCLK tsu(SCLK-RXD) th(SCLK-RXD) RXD td(SCLK-TXD) 0.8 VCC 0.2 VCC tv(SCLK-TXD) TXD Fig. 3.1.2 Timing diagram (in single-chip mode) 3-12 3800 GROUP USER'S MANUAL APPENDIX 3.1 Electrical characteristics Timing Diagram in Memory Expansion Mode and Microprocessor Mode (1) tC() tWH() tWL() 0.5 VCC td(-AH) tv(-AH) 0.5 VCC AD15-AD8 td(-AL) tv(-AL) 0.5 VCC AD7-AD0 td(-SYNC) tv(-SYNC) SYNC 0.5 VCC td(-WR) tv(-WR) RD,WR tSU(ONW-) 0.5 VCC th(-ONW) ONW 0.8 VCC 0.2 VCC tSU(DB-) th(-DB) DB0-DB7 (At CPU reading) DB0-DB7 (At CPU writing) Timing Diagram in Microprocessor Mode 0.8 VCC 0.2 VCC td(-DB) 0.5 VCC tv(-DB) RESET 0.8 VCC 0.2 VCC 0.5 VCC td(RESET- RESET OUT) tv(- RESETOUT) RESETOUT 0.5 VCC Fig. 3.1.3 Timing diagram (in memory expansion mode and microprocessor mode) (1) 3800 GROUP USER'S MANUAL 3-13 APPENDIX 3.1 Electrical characteristics Timing Diagram in Memory Expansion Mode and Microprocessor Mode (2) tWL(RD) tWL(WR) RD,WR td(AH-RD) td(AH-WR) 0.5 VCC tv(RD-AH) tv(WR-AH) AD15-AD8 0.5 VCC td(AL-RD) td(AL-WR) tv(RD-AL) tv(WR-AL) AD7-AD0 0.5 VCC tsu(ONW-RD) tsu(ONW-WR) th(RD-ONW) th(WR-ONW) ONW (At CPU reading) RD 0.8 VCC 0.2 VCC tWL(RD) 0.5 VCC tSU(DB-RD) th(RD-DB) DB0-DB7 0.8 VCC 0.2 VCC (At CPU writing) WR td(WR-DB) 0.5 VCC tWL(WR) tv(WR-DB) 0.5 VCC DB0-DB7 Fig. 3.1.4 Timing diagram (in memory expansion mode and microprocessor mode) (2) 3-14 3800 GROUP USER'S MANUAL APPENDIX 3.2 Standard characteristics 3.2 Standard characteristics 3.2.1 Power source current characteristic examples Figures 3.2.1 and Figure 3.2.2 show power source current characteristic examples. [Measuring condition : 25 C] Rectangular waveform Power source current (mA) 8 Vcc = 5.5 V, Ta = 25 7 6 5 4 3 2 1 0 Vcc = 3.0 V, Ta = 25 Vcc = 4.0 V, Ta = 25 0 1 2 3 4 5 6 7 8 Frequency f(XIN) (MHz) Fig. 3.2.1 Power source current characteristic example [Measuring condition : 25 C] Rectangular waveform Power source current (mA) 8 7 6 5 4 3 2 1 Vcc = 3.0 V, Ta = 25 0 0 1 2 3 4 5 6 7 8 Frequency f(XIN) (MHz) Vcc = 5.5 V, Ta = 25 Vcc = 4.0 V, Ta = 25 Fig. 3.2.2 Power source current characteristic example (in wait mode) 3800 GROUP USER'S MANUAL 3-15 APPENDIX 3.2 Standard characteristics 3.2.2 Port standard characteristic examples Figures 3.2.3, Figure 3.2.4, Figure 3.2.5 and Figure 3.2.6 show port standard characteristic examples. [Port P00 IOH-VOH characteristic (P-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P7) IOH (mA) - 50 - 45 - 40 - 35 - 30 - 25 - 20 - 15 - 10 -5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc = 3.0 V, Ta = 90 Vcc = 4.0 V, Ta = 90 Vcc = 5.0 V, Ta = 90 VOH (V) Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive (1) [Port P00 IOH-VOH characteristic (P-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P7) IOH (mA) - 50 - 45 - 40 - 35 - 30 - 25 - 20 - 15 - 10 -5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc = 3.0 V, Ta = 25 Vcc = 4.0 V, Ta = 25 Vcc = 5.0 V, Ta = 25 VOH (V) Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive (2) 3-16 3800 GROUP USER'S MANUAL APPENDIX 3.2 Standard characteristics [Port P00 IOL-VOL characteristic (N-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P7) IOL (mA) 50 45 40 35 30 25 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Vcc = 3.0 V, Ta = 90 Vcc = 4.0 V, Ta = 90 Vcc = 5.0 V, Ta = 90 VOL (V) Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive (1) [Port P00 IOL-VOL characteristic (N-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P7) IOL (mA) 60 55 50 45 40 35 30 25 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Vcc = 3.0 V, Ta = 25 Vcc = 4.0 V, Ta = 25 Vcc = 5.0 V, Ta = 25 VOL (V) Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive (2) 3800 GROUP USER'S MANUAL 3-17 APPENDIX 3.3 Notes on use 3.3 Notes on use 3.3.1 Notes on interrupts (1) Sequence for switching an external interrupt detection edge When the external interrupt detection edge must be switched, make sure the following sequence. Reason The interrupt circuit recognizes the switching of the detection edge as the change of external input signals. This may cause an unnecessary interrupt. Clear an interrupt enable bit to "0" (interrupt disabled) Switch the detection edge Clear an interrupt request bit to "0" (no interrupt request issued) Set the interrupt enable bit to "1" ( interrupt enabled ) (2) Bits 7 and 6 of the interrupt control register 2 Fix the bits 7 and 6 of the interrupt control register 2 (Address:003F16) to "0". Figure 3.3.1 shows the structure of the interrupt control register 2. b7 b0 Interrupt control register 2 Address 003F16 00 Interrupt enable bits Not used Fix these bits to "0". Fig. 3.3.1 Structure of interrupt control register 2 3.3.2 Notes on the serial I/O (1) Stop of data transmission As for the serial I/O that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the transmit enable bit to "0" (transmit disabled), and clear the serial I/O enable bit to "0" (serial I/O disabled)in the following cases : q when stopping data transmission during transmitting data in the clock synchronous serial I/O mode q when stopping data transmission during transmitting data in the UART mode q when stopping only data transmission during transmitting and receiving data in the UART mode Reason Since transmission is not stopped and the transmission circuit is not initialized even if the serial I/O enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, the data is transferred to the transmit shift register and start tp be sjifted. When the serial I/O enable bit is set to "1" at this time, the data during internally shifting is output to the TxD pin and ti may cause an operation failure to a microcomputer. (2) Stop of data reception As for the serial I/O that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the receive enable bit to "0" (receive disabled), or clear the serial I/O enable bit to "0" (serial I/O disabled) in the following case : q when stopping data reception during receiving data in the clock synchronous serial I/O mode Clear the receive enable bit to "0" (receive disabled) in the following cases : q when stopping data reception during receiving data in the UART mode q when stopping only data reception during transmitting and receiving data in the UART mode 3-18 3800 GROUP USER'S MANUAL APPENDIX 3.3 Notes on use (3) Stop of data transmission and reception in a clock synchronous serial I/O mode As for the serial I/O that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear both the transmit enable bit and receive enable bit to "0" (transmit and receive disabled) at the same time in the following case: q when stopping data transmission and reception during transmitting and receiving data in the clock synchronous mode (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to "0" (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O enable bit to "0" (serial I/O disabled) (refer to (1)). (4) The SRDY pin on a receiving side When signals are output from the SRDY pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and the transmit enable bit to "1" (transmit enabled). (5) Stop of data reception in a clock synchronous serial I/O mode Set the serial I/O control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0." Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Set the bits 0 to 3 and bit 6 of the serial I/O control register Can be set with the LDM instruction at the same time Set both the transmit enable bit (TE) and the receive enable bit (RE) to "1" (6) Control of data transmission using the transmit shift completion flag The transmit shift completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When checking the transmit shift completion flag after writing a data to the transmit buffer register for controlling a data transmission, note this delay. (7) Control of data transmission using an external clock When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to "1" at "H" level of the SCLK input signal. Also, write data to the transmit buffer register at "H" level of the SCLK input signal. 3.3.3 Notes on the RESET pin When a rising time of the reset signal is long, connect a ceramic capacitor or others across the RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, make sure the following : qMake the length of the wiring which is connected to a capacitor the shortest possible. qMake sure to check the operation of application products on the user side. Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, a microcomputer may malfunction. 3800 GROUP USER'S MANUAL 3-19 APPENDIX 3.3 Notes on use 3.3.4 Notes on input and output pins (1) Fix of a port input level in stand-by state Fix input levels of an input and an I/O port for getting effect of low-power dissipation in stand-by state*, especially for the I/O ports of the N-channel open-drain. Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, make sure the following: qExternal circuit qVariation of output levels during the ordinary operation * stand-by state : the stop mode by executing the STP instruction the wait mode by executing the WIT instruction Reason Even when setting as an output port with its direction register, in the following state : qN-channel......when the content of the port latch is "1" the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Make sure that the level becomes "undefined" depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input and an I/O port are "undefined." This may cause power source current. (2) Modify of the content of I/O port latch When the content of the port latch of an I/O port is modified with the bit managing instruction*, the value of the unspecified bit may be changed. Reason The bit managing instruction is read-modify-write instruction for reading and writing data by a byte unit. Accordingly, when this instruction is executed on one bit of the port latch of an I/O port, the following is executed to all bits of the port latch. qAs for a bit which is set as an input port : The pin state is read in the CPU, and is written to this bit after bit managing. qAs for a bit which is set as an output port : The bit value is read in the CPU, and is written to this bit after bit managing. Make sure the following : qEven when a port which is set as an output port is changed for an input port, its port latch holds the output data. qEven when a bit of a port latch which is set as an input port is not speccified with a bit managing instruction, its value may be changed in case where content of the pin differs from a content of the port latch. * bit managing instructions : SEB and CLB instruction 3-20 3800 GROUP USER'S MANUAL APPENDIX 3.3 Notes on use 3.3.5 Notes on memory expansion mode and microprocessor mode (1) Writing data to the port latch of port P3 In the memory expansion or the microprocessor mode, ports P30 and P31 can be used as the output port. Use the LDM or STA instruction for writing data to the port latch (address 000616) of port P3. When using a read-modify-write instruction (the SEB or the CLB instruction), allocate the read and the write enabled memory at address 000616. Reason In the memory expansion or microprocessor mode, address 000616 is allocated in the external area. Accordingly, L Data is read from the external memory. L Data is written to both the port latch of the port P3 and the external memory. Accordingly, when executing a read-modify-write instruction for address 000616, external memory data is read and modified, and the result is written in both the port latch of the port P3 and the external memory. If the read enabled memory is not allocated at address 000616, the read data is undefined. The undefined data is modified and written to the port latch of the port P3. The port latch data of port P3 becomes "undefined." (2) Overlap of an internal memory and an external memory When the internal and the external memory are overlapped in the memory expansion mode, the internal memory is valid in this overlapped area. When the CPU writes or reads to this area, the following is performed : L When reading data Only the data in the internal memory is read into the CPU and the data in the external memory is not read into the CPU. However, as the read signal and address are still valid, the external memory data of the corresponding address is output to the external data bus. L When writing data Data is written in both the internal and the external memory. 3800 GROUP USER'S MANUAL 3-21 APPENDIX 3.3 Notes on use 3.3.6 Notes on built-in PROM (1) Programming adapter To write or read data into/from the internal PROM, use the dedicated programming adapter and general-purpose PROM programmer as shown in Table 3.3.1. Table 3.3.1 Programming adapter Microcomputer M38002E4SS M38004E8SS M38002E2SP M38002E4SP M38004E8SP (one-time blank) M38002E4DSP (one-time blank) M38002E4FS PCA4738L-64A M38004E8FS M38002E2FP M38002E4FP M38004E8FP PCA4738F-64A (one-time blank) M38002E4DFP (one-time blank) (2) Write and read In PROM mode, operation is the same as that of the M5M27C256AK, but programming conditions of PROM programmer are not set automatically because there are no internal device ID codes. Accurately set the following conditions for data write/read. Take care not to apply 21 V to Vpp pin (is also used as the CNVSS pin), or the product may be permanently damaged. q Programming voltage : 12.5 V q Setting of programming adapter switch : refer to table 3.3.2 q Setting of PROM programmer address : refer to table 3.3.3 Table 3.3.2 Setting of programming adapter switch Programming adapter PCA4738S-64A PCA4738L-64A PCA4738F-64A CMOS CMOS OFF SW 1 SW 2 SW 3 PCA4738S-64A Programming adapter 3-22 3800 GROUP USER'S MANUAL APPENDIX 3.3 Notes on use Table 3.3.3 Setting of PROM programmer address Microcomputer M38002E2SP M38002E2FP M38002E4SS M38002E4SP M38002E4FS M38002E4FP M38002E4DSP M38002E4DFP M38004E8SS M38004E8SP M38004E8FS M38004E8FP Note1 : Addresses E08016 to FFFD16 in the internal PROM correspond to addresses 608016 to 7FFD16 in the ROM programmer. 2 : Addresses C08016 to FFFD16 in the internal PROM correspond to addresses 408016 to 7FFD16 in the ROM programmer. 3 : Addresses 808016 to FFFD16 in the internal PROM correspond to addresses 008016 to 7FFD16 in the ROM programmer. (3) Erasing Contents of the windowed EPROM are erased through an ultraviolet light source of the wavelength 2537Angstrom . At least 15 W-sec/cm 2 are required to erase EPROM contents. Address : 008016 (Note 3) Address : 7FFD16 (Note 3) Address : 408016 (Note 2) Address : 7FFD16 (Note 2) PROM programmer start address Address : 608016 (Note 1) PROM programmer completion address Address : 7FFD16 (Note 1) 3800 GROUP USER'S MANUAL 3-23 APPENDIX 3.4 Countermeasures against noise 3.4 Countermeasures against noise Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 Shortest wiring length The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Wiring for the RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). Reason The reset works to initialize a microcomputer. The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit VSS RESET VSS Reset circuit VSS RESET VSS N.G. 3800 group O.K. 3800 group Fig. 3.4.1 Wiring for the RESET pin (2) Wiring for clock input/output pins qMake the length of wiring which is connected to clock I/O pins as short as possible. qMake the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillatorand the VSS pin of a microcomputer as short as possible. qSeparate the VSS pattern only for oscillation from other VSS patterns. Reason A microcomputer's operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. 3-24 3800 GROUP USER'S MANUAL APPENDIX 3.4 Countermeasures against noise Noise An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example XIN XOUT VSS XIN XOUT VSS XIN XOUT VSS N.G. Fig. 3.4.2 Wiring for clock I/O pins O.K. Separate the VSS line for oscillation from other VSS lines (3) Wiring for the VPP pin of the One Time PROM version and the EPROM version (In this microcomputer the VPP pin is also used as the CNVSS pin) Connect an approximately 5 k resistor to the V P P pin the shortest possible in series and also to the VSS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the VSS pin the shortest possible. Note:Even when a circuit which inclued an approximately 5 k resistor is used in the Mask ROM version, the maicrocomputer operates correctly. Reason The VPP pin of the One Time PROM and the EPROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for wiring flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal in struction codes or data are read from the built-in PROM, which may cause a program runaway. Approximately 5k CNVSS/VPP VSS 3800 group Make it the shortest possible Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM and the EPROM version 3.4.2 Connection of a bypass capacitor across the Vss line and the Vcc line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VCC line as follows: qConnect a bypass capacitor across the VSS pin and the VCC pin at equal length . qConnect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. qUse lines with a larger diameter than other signal lines for VSS line and VCC line. VCC Chip VCC VSS VSS Fig. 3.4.4 Bypass capacitor across the VSS line and the VCC line 3800 GROUP USER'S MANUAL 3-25 APPENDIX 3.4 Countermeasures against noise 3.4.3. Consideration for oscillator Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping an oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Keeping an oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an osillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Reason Signal lines where potential levels change frequently (such as the CNTR pin line) may affect other lines at signal rising or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. Microcomputer Mutual inductance M Large current GND Fig.3.4.5 Wiring for a large current signal line XIN XOUT VSS Do not cross CNTR XIN XOUT VSS Fig.3.4.6 Wiring to a signal line where potential levels change frequently 3.4.4 Setup for I/O ports Setup I/O ports using hardware and software as follows: O.K. Direction register Noise Noise N.G. 3-26 3800 GROUP USER'S MANUAL APPENDIX 3.4 Countermeasures against noise 3.4.5 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. Main routine (SWDT) N CLI Main processing N (SWDT) =N? =N Interrupt processing routine (SWDT) (SWDT)--1 Interrupt processing >0 RTI Return Main routine (SWDT) 0? 0 Interrupt processing routine errors errors As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. qWatches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing count after the initial value N has been set. qDetects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following cases: If the SWDT contents do not change after interrupt processing 3800 GROUP USER'S MANUAL 3-27 APPENDIX 3.5 List of registers 3.5 List of registers Port Pi b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6, 7) [Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16] B 0 Port Pi0 1 Port Pi1 Name q Function In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins (Note) At reset RW ? ? ? ? ? ? ? ? q 2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7 Note : Port P7 register [Address : 0E16] Port P7 is a 2-bit port (P70, P71). Accordingly, when bits 2 to 7 are read out, the contents are "0." Fig. 3.5.1 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 7) Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i =0, 1, 2, 3, 4, 5, 6, 7) [Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16, 0F16] B Name Function 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode (Note) (Note) (Note) (Note) (Note) (Note) At reset RW ! ! ! ! ! ! ! ! 0 Port Pi direction register 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Note : Port P7 direction register [Address : 0F16] Port P7 is a 2-bit port (P70, P71). Accordingly, these bits do not have a direction register function. Fig. 3.5.2 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6, 7) 3-28 3800 GROUP USER'S MANUAL APPENDIX 3.5 List of registers Transmit/Receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 Transmit/Receive buffer register (TB/RB) [Address : 1816] B Function from this buffer register. * At writing : a data is written to the Transmit buffer register. * At reading : a content of the Receive buffer register is read out. At reset RW 0 A transmission data is written to or a receive data is read out 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? Note : A content of the Transmit buffer register cannot be read out. A data cannot be written to the Receive buffer register. Fig. 3.5.3 Structure of Transmit/Receive buffer register Serial I/O status register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O status reigster (SIOSTS) [Address : 1916] B 0 Name Transmit buffer empty flag (TBE) Function 0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error 0 : (OE) (PE) (FE) = 0 1 : (OE) (PE) (FE) = 1 At reset RW ! ! ! ! ! ! ! ! 0 0 0 0 0 0 0 1 1 Receive buffer full flag (RBF) 2 Transmit shift register shift completion flag (TSC) 3 Overrun error flag (OE) 4 Parity error flag (PE) 5 Framing error flag (FE) 6 Summing error flag (SE) 7 Nothing is allocated for this bit. It is a write disabled bit. When this bit is read out, the value is "0." Fig. 3.5.4 Structure of Serial I/O status register 3800 GROUP USER'S MANUAL 3-29 APPENDIX 3.5 List of registers Serial I/O control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register (SIOCON) [Address : 1A16] Name B 0 BRG count source Function 0 : f(XIN) 1 : f(XIN)/4 At selecting clock synchronous serial I/O 0 : BRG output divided by 4 1 : External clock input At selecting UART 0 : BRG output divided by 16 1 : External clock input divided by 16 At reset RW 0 0 selection bit (CSS) Serial I/O synchronous clock 1 selection bit (SCS) 2 SRDY output enable bit (SRDY) 3 Transmit interrupt source selection bit (TIC) 4 Transmit enable bit (TE) 5 Receive enable bit (RE) 6 Serial I/O mode selection bit (SIOM) 7 Serial I/O enable bit (SIOE) 0 : I/O port (P47) 1 : SRDY output pin 0 : Transmit buffer empty 1 : Transmit shift operating completion 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : UART 1 : Clock synchronous serial I/O 0 : Serial I/O disabled (P44-P47 : I/O port) 1 : Serial I/O enabled (P44-P47 : Serial I/O function pin) 0 0 0 0 0 0 Fig. 3.5.5 Structure of Serial I/O control register UART control register b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UARTCON) [Address : 1B16] B Name Character length 0 1 2 3 4 Function At reset RW 5 6 7 0 : 8 bits selection bit (CHAS) 1 : 7 bits 0 : Parity checking disabled Parity enable bit (PARE) 1 : Parity checking enabled 0 : Even parity Parity selection bit (PARS) 1 : Odd parity 0 : 1 stop bit Stop bit length selection bit (STPS) 1 : 2 stop bits In output mode P45/TxD P-channel 0 : CMOS output output disable bit 1 : N-channel open-drain (POFF) output Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "1." 0 0 0 0 0 1 1 1 5 5 5 Fig. 3.5.6 Structure of UART control register 3-30 3800 GROUP USER'S MANUAL APPENDIX 3.5 List of registers Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator (BRG) [Address : 1C16] Function B 0 A count value of Baud rate generator is set. 1 2 3 4 5 6 7 At reset RW ? ? ? ? ? ? ? ? Fig. 3.5.7 Structure of Baud rate generator Prescaler 12, Prescaler X, Prescaler Y b7 b6 b5 b4 b3 b2 b1 b0 Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY) [Address : 2016, 2416, 2616] B 0 1 2 3 4 5 6 7 Function q q q At reset RW The count value of each prescaler is set. The value set in this register is written to both the prescaler and the prescaler latch at the same time. When the prescaler is read out, the value (count value) of the prescaler is read out. 1 1 1 1 1 1 1 1 Fig. 3.5.8 Structure of Prescaler 12, Prescaler X, Prescaler Y 3800 GROUP USER'S MANUAL 3-31 APPENDIX 3.5 List of registers Timer 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1) [Address : 2116] B 0 1 2 3 4 5 6 7 Function q q q At reset RW The count value of the Timer 1 is set. The value set in this register is written to both the Timer 1 and the Timer 1 latch at the same time. When the Timer 1 is read out, the value (count value) of the Timer 1 is read out. 1 0 0 0 0 0 0 0 Fig. 3.5.9 Structure of Timer 1 Timer 2, Timer X, Timer Y b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2), Timer X (TX), Timer Y (TY) [Address : 2216, 2516, 2716] B 0 1 2 3 4 5 6 7 q q q Function The count value of each timer is set. The value set in this register is written to both the Timer and the Timer latch at the same time. When the Timer is read out, the value (count value) of the Timer is read out. At reset RW 1 1 1 1 1 1 1 1 Fig. 3.5.10 Structure of Timer 2, Timer X, Timer Y 3-32 3800 GROUP USER'S MANUAL APPENDIX 3.5 List of registers Timer XY mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer XY mode register (TM) [Address : 2316] Name B 0 Timer X operating mode bit Function b1 b0 At reset RW 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 1 : Pulse width measurement mode 2 CNTR0 active edge switch bit It depends on the operating mode of the Timer X (refer to Table 3.5.1). 0 : Count start 3 Timer X count stop bit 1 : Count stop 0 0 0 0 0 0 0 0 4 Timer Y operating mode bit 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 5 1 1 : Pulse width measurement mode 6 CNTR1 active edge switch bit It depends on the operating mode of the Timer Y (refer to Table 3.5.1). 0 : Count start 7 Timer Y count stop bit 1 : Count stop b5 b4 Fig. 3.5.11 Structure of Timer XY mode register Table. 3.5.1 Function of CNTR0/CNTR1 edge switch bit Operating mode of Timer X/Timer Y Timer mode Function of CNTR0/CNTR1 edge switch bit (bits 2 and 6) "0" "1" Pulse output mode "0" "1" Event counter mode "0" "1" Pulse width measurement mode "0" "1" * Generation of CNTR0/CNTR1 interrupt request : Falling (No effect on timer count) * Generation of CNTR0/CNTR1 interrupt request : Rising (No effect on timer count) * Start of pulse output : From "H" level * Generation of CNTR0/CNTR1 interrupt request : Falling * Start of pulse output : From "L" level * Generation of CNTR0/CNTR1 interrupt request : Rising * Timer X/Timer Y : Count of rising edge * Generation of CNTR0/CNTR1 interrupt request : Falling * Timer X/Timer Y : Count of falling edge * Generation of CNTR0/CNTR1 interrupt request : Rising * Timer X/Timer Y : Measurement of "H" level width * Generation of CNTR0/CNTR1 interrupt request : Falling * Timer X/Timer Y : Measurement of "L" level width * Generation of CNTR0/CNTR1 interrupt request : Rising edge edge edge edge edge edge edge edge 3800 GROUP USER'S MANUAL 3-33 APPENDIX 3.5 List of registers Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A16] Name B 0 INT0 interrupt edge 1 selection bit INT1 interrupt edge selection bit selection bit INT3 interrupt edge selection bit Function 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active At reset RW 0 0 0 0 0 0 0 0 ! ! 2 INT2 interrupt edge 3 4 INT4 interrupt edge 5 6 7 selection bit 0 : Falling edge active INT5 interrupt edge 1 : Rising edge active selection bit Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0." Fig. 3.5.12 Structure of Interrupt edge selection register CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Adress : 3B16] Name B 0 Processor mode bits 1 2 Stack page selection bit Function 00 : Single-chip mode 01 : Memory expansion mode 10 : Microprocessor mode 11 : Not available 0 : 0 page 1 : 1 page At reset RW 0 T 0 0 0 0 0 0 ! ! ! ! ! ! 3 4 5 6 7 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0." T An initial value of bit 1 is determined by a level of the CNVSS pin. Fig. 3.5.13 Structure of CPU mode register 3-34 3800 GROUP USER'S MANUAL APPENDIX 3.5 List of registers Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 1 (IREQ1) [Address : 3C16] B Name Function 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request At reset RW T T T T T T T T 0 INT0 interrupt request bit 1 INT1 interrupt request bit 2 Serial I/O receive interrupt request bit 0 0 0 0 0 0 0 0 3 Serial I/O transmit interrupt request bit bit 4 Timer X interrupt request 5 Timer Y interrupt request bit Timer 1 interrupt request bit 6 7 Timer 2 interrupt request bit 0 : No interrupt request 1 : Interrupt request T "0" is set by software, but not "1." Fig. 3.5.14 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address : 3D16] B Name Function 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request At reset RW T T T T T T ! ! 0 CNTR0 interrupt request bit 1 CNTR1 interrupt request bit 2 INT2 interrupt request bit 3 INT3 interrupt request bit 4 5 6 7 0 0 0 0 0 0 0 0 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request INT4 interrupt request bit 1 : Interrupt request 0 : No interrupt request INT5 interrupt request bit 1 : Interrupt request Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0." T "0" is set by software, but not "1." Fig. 3.5.15 Structure of Interrupt request register 2 3800 GROUP USER'S MANUAL 3-35 APPENDIX 3.5 List of registers Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 INT0 interrupt enable bit 1 INT1 interrupt enable bit enable bit 3 Serial I/O transmit interrupt enable bit 4 Timer X interrupt enable bit 0 0 0 0 0 0 0 0 2 Serial I/O receive interrupt 5 Timer Y interrupt enable bit 6 Timer 1 interrupt enable bit 7 Timer 2 interrupt enable bit Fig. 3.5.16 Structure of Interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 00 Interrupt control reigster 2 (ICON2) [Address : 3F16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 CNTR0 interrupt enable bit 1 CNTR1 interrupt enable bit 2 INT2 interrupt enable bit 3 INT3 interrupt enable bit 4 INT4 interrupt enable bit 5 INT5 interrupt enable bit 6 Fix these bits to "0." 7 0 0 0 0 0 0 0 0 Fig. 3.5.17 Structure of Interrupt control register 2 3-36 3800 GROUP USER'S MANUAL APPENDIX 3.6 Mask ROM ordering method 3.6 Mask ROM ordering method GZZ-SH04-34B<13B0> Mask ROM number Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor g Customer g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M38002M2-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M38002M2-XXXFP (hexadecimal notation) 27256 EPROM address 000016 Product name 000F16 001016 607F16 608016 7FFD16 7FFE16 7FFF16 ASCII code : `M38002M2-' 27512 EPROM address 000016 Product name 000F16 001016 E07F16 E08016 FFFD16 FFFE16 FFFF16 ASCII code : `M38002M2-' In the address space of the microcomputer, the internal ROM area is from address E08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. data ROM 8062 bytes data ROM 8062 bytes (1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38002M2-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M2-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature Address 000016 000116 000216 000316 000416 000516 000616 000716 `M' = 4D16 `3' = 3316 `8' = 3816 `0' = 3016 `0' = 3016 `2' = 3216 `M' = 4D16 `2' = 3216 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) 3800 GROUP USER'S MANUAL 3-37 APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-34B<13B0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M2-XXXSP/FP MITSUBISHI ELECTRIC We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27256 *=a$8000 .BYTEa `M38002M2-' 27512 *=a$0000 .BYTEa `M38002M2-' Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (64P4B for M38002M2-XXXSP, 64P6N for M38002M2-XXXFP) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator External clock input At what frequency? Quartz crystal Other ( f(XIN) = ) MHz (2) In which operation mode will you use your microcomputer? Single-chip mode Microprocessor mode Memory expansion mode g 4. Comments (2/2) 3-38 3800 GROUP USER'S MANUAL APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-79B<16A0> Mask ROM number Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor g Customer g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M38002M2DXXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M38002M2DXXXFP (hexadecimal notation) 27256 EPROM address 000016 Product name 000F16 001016 607F16 608016 7FFD16 7FFE16 7FFF16 ASCII code : `M38002M2D' 27512 EPROM address 000016 Product name 000F16 001016 E07F16 E08016 FFFD16 FFFE16 FFFF16 ASCII code : `M38002M2D' In the address space of the microcomputer, the internal ROM area is from address E08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. data ROM 8062 bytes data ROM 8062 bytes (1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38002M2D" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M2DXXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature `M' = 4D16 `3' = 3316 `8' = 3816 `0' = 3016 `0' = 3016 `2' = 3216 `M' = 4D16 `2' = 3216 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 `D' = 4416 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) 3800 GROUP USER'S MANUAL 3-39 APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-79B<16A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M2DXXXSP/FP MITSUBISHI ELECTRIC We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27256 *=a$8000 .BYTEa `M38002M2D' 27512 *=a$0000 .BYTEa `M38002M2D' Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (64P4B for M38002M2DXXXSP, 64P6N for M38002M2DXXXFP) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator External clock input At what frequency? Quartz crystal Other ( f(XIN) = ) MHz (2) In which operation mode will you use your microcomputer? Single-chip mode Microprocessor mode Memory expansion mode g 4. Comments (2/2) 3-40 3800 GROUP USER'S MANUAL APPENDIX 3.6 Mask ROM ordering method GZZ-SH03-22B<9YB0> Mask ROM number Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor g Customer g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M38002M4-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M38002M4-XXXFP (hexadecimal notation) 27256 EPROM address 000016 Product name 000F16 001016 407F16 408016 7FFD16 7FFE16 7FFF16 ASCII code : `M38002M4-' 27512 EPROM address 000016 Product name 000F16 001016 C07F16 C08016 FFFD16 FFFE16 FFFF16 ASCII code : `M38002M4-' In the address space of the microcomputer, the internal ROM area is from address C08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. data ROM 16254 bytes data ROM 16254 bytes (1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38002M4-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M4-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature Address 000016 000116 000216 000316 000416 000516 000616 000716 `M' = 4D16 `3' = 3316 `8' = 3816 `0' = 3016 `0' = 3016 `2' = 3216 `M' = 4D16 `4' = 3416 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) 3800 GROUP USER'S MANUAL 3-41 APPENDIX 3.6 Mask ROM ordering method GZZ-SH03-22B<9YB0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M4-XXXSP/FP MITSUBISHI ELECTRIC We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27256 *=a$8000 .BYTEa `M38002M4-' 27512 *=a$0000 .BYTEa `M38002M4-' Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (64P4B for M38002M4-XXXSP, 64P6N for M38002M4-XXXFP) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator External clock input At what frequency? Quartz crystal Other ( f(XIN) = ) MHz (2) In which operation mode will you use your microcomputer? Single-chip mode Microprocessor mode Memory expansion mode g 4. Comments (2/2) 3-42 3800 GROUP USER'S MANUAL APPENDIX 3.6 Mask ROM ordering method GZZ-SH05-12B<21A0> Mask ROM number Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor g Customer g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M38002M4DXXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M38002M4DXXXFP (hexadecimal notation) 27256 EPROM address 000016 Product name 000F16 001016 407F16 408016 7FFD16 7FFE16 7FFF16 ASCII code : `M38002M4D' 27512 EPROM address 000016 Product name 000F16 001016 C07F16 C08016 FFFD16 FFFE16 FFFF16 ASCII code : `M38002M4D' In the address space of the microcomputer, the internal ROM area is from address C08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. data ROM 16254 bytes data ROM 16254 bytes (1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38002M4D" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M4DXXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature `M' = 4D16 `3' = 3316 `8' = 3816 `0' = 3016 `0' = 3016 `2' = 3216 `M' = 4D16 `4' = 3416 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 `D' = 4416 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) 3800 GROUP USER'S MANUAL 3-43 APPENDIX 3.6 Mask ROM ordering method GZZ-SH05-12B<21A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M4DXXXSP/FP MITSUBISHI ELECTRIC We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27256 *=a$8000 .BYTEa `M38002M4D' 27512 *=a$0000 .BYTEa `M38002M4D' Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (64P4B for M38002M4DXXXSP, 64P6N for M38002M4DXXXFP) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator External clock input At what frequency? Quartz crystal Other ( f(XIN) = ) MHz (2) In which operation mode will you use your microcomputer? Single-chip mode Microprocessor mode Memory expansion mode g 4. Comments (2/2) 3-44 3800 GROUP USER'S MANUAL APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-62B<14B0> Mask ROM number Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor g Customer g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M38003M6-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M38003M6-XXXFP M38003M6-XXXHP (hexadecimal notation) 27256 EPROM address 000016 Product name 000F16 001016 207F16 208016 7FFD16 7FFE16 7FFF16 ASCII code : `M38003M6-' 27512 EPROM address 000016 Product name 000F16 001016 A07F16 A08016 FFFD16 FFFE16 FFFF16 ASCII code : `M38003M6-' In the address space of the microcomputer, the internal ROM area is from address A08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. data ROM 24446 bytes data ROM 24446 bytes (1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38003M6-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38003M6-XXXSP/FP/HP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature `M' = 4D16 `3' = 3316 `8' = 3816 `0' = 3016 `0' = 3016 `3' = 3316 `M' = 4D16 `6' = 3616 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) 3800 GROUP USER'S MANUAL 3-45 APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-62B<14B0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38003M6-XXXSP/FP/HP MITSUBISHI ELECTRIC We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27256 *=a$8000 .BYTEa `M38003M6-' 27512 *=a$0000 .BYTEa `M38003M6-' Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (64P4B for M38003M6-XXXSP, 64P6N for M38003M6-XXXFP) and attach it to the mask ROM confirmation form. M38003M6-XXXHP is specified to the standard mark. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator External clock input At what frequency? Quartz crystal Other ( f(XIN) = ) MHz (2) In which operation mode will you use your microcomputer? Single-chip mode Microprocessor mode Memory expansion mode g 4. Comments (2/2) 3-46 3800 GROUP USER'S MANUAL APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-30B<13B0> Mask ROM number Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor g Customer g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M38004M8-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M38004M8-XXXFP (hexadecimal notation) 27512 EPROM address 000016 Product name 000F16 001016 807F16 808016 FFFD16 FFFE16 FFFF16 ASCII code : `M38004M8-' In the address space of the microcomputer, the internal ROM area is from address 808016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. data ROM 32638 bytes (1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38004M8-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38004M8-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature `M' = 4D16 `3' = 3316 `8' = 3816 `0' = 3016 `0' = 3016 `4' = 3416 `M' = 4D16 `8' = 3816 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) 3800 GROUP USER'S MANUAL 3-47 APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-30B<13B0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38004M8-XXXSP/FP MITSUBISHI ELECTRIC assembier We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27512 *=a$0000 .BYTEa `M38004M8-' Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (64P4B for M38004M8-XXXSP, 64P6N for M38004M8-XXXFP) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator External clock input At what frequency? Quartz crystal Other ( f(XIN) = ) MHz (2) In which operation mode will you use your microcomputer? Single-chip mode Microprocessor mode Memory expansion mode g 4. Comments (2/2) 3-48 3800 GROUP USER'S MANUAL APPENDIX 3.6 Mask ROM ordering method GZZ-SH07-23B<33A0> Mask ROM number Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor g Customer g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M38004M8DXXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M38004M8DXXXFP (hexadecimal notation) 27512 EPROM address 000016 Product name 000F16 001016 807F16 808016 FFFD16 FFFE16 FFFF16 ASCII code : `M38004M8D' In the address space of the microcomputer, the internal ROM area is from address 808016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. data ROM 32638 bytes (1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38004M8D" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38004M8DXXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature `M' = 4D16 `3' = 3316 `8' = 3816 `0' = 3016 `0' = 3016 `4' = 3416 `M' = 4D16 `8' = 3816 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 `D' = 4416 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) 3800 GROUP USER'S MANUAL 3-49 APPENDIX 3.6 Mask ROM ordering method GZZ-SH07-23B<33A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38004M8DXXXSP/FP MITSUBISHI ELECTRIC assembier We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27512 *=a$0000 .BYTEa `M38004M8D' Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (64P4B for M38004M8DXXXSP, 64P6N for M38004M8DXXXFP) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator External clock input At what frequency? Quartz crystal Other ( f(XIN) = ) MHz (2) In which operation mode will you use your microcomputer? Single-chip mode Microprocessor mode Memory expansion mode g 4. Comments (2/2) 3-50 3800 GROUP USER'S MANUAL APPENDIX 3.7 Mark specification form 3.7 Mark specification form 3800 GROUP USER'S MANUAL 3-51 APPENDIX 3.7 Mark specification form 3-52 3800 GROUP USER'S MANUAL APPENDIX 3.8 Package outline 3.8 Package outline 2.5/1 2.5/1 3800 GROUP USER'S MANUAL 3-53 APPENDIX 3.8 Package outline 2.5/1 1.5/1 3-54 3800 GROUP USER'S MANUAL APPENDIX 3.8 Package outline 1.5/1 3800 GROUP USER'S MANUAL 3-55 APPENDIX 3.9 Machine instructions 3.9 Machine instructions Addressing mode Symbol Function Details IMP OP n ADC (Note 1) (Note 5) When T = 0 AA+M+C When T = 1 M(X) M(X) + M + C Adds the carry, accumulator and memory contents. The results are entered into the accumulator. Adds the contents of the memory in the address indicated by index register X, the contents of the memory specified by the addressing mode and the carry. The results are entered into the memory at the address indicated by index register X. "AND's" the accumulator and memory contents. The results are entered into the accumulator. "AND's" the contents of the memory of the address indicated by index register X and the contents of the memory specified by the addressing mode. The results are entered into the memory at the address indicated by index register X. Shifts the contents of accumulator or contents of memory one bit to the left. The low order bit of the accumulator or memory is cleared and the high order bit is shifted into the carry flag. Branches when the contents of the bit specified in the accumulator or memory is "0". Branches when the contents of the bit specified in the accumulator or memory is "1". Branches when the contents of carry flag is "0". Branches when the contents of carry flag is "1". Branches when the contents of zero flag is "1". 24 3 2 IMM # OP n 69 2 A # OP n 2 BIT, A # OP n ZP # OP n 65 3 BIT, ZP # OP n 2 # ASL C 7 0 0 BBC (Note 4) BBS (Note 4) BCC (Note 4) BCS (Note 4) BEQ (Note 4) BIT Ab or Mb = 0? Ab or Mb = 1? C = 0? C = 1? Z = 1? V A M BMI (Note 4) BNE (Note 4) BPL (Note 4) BRA N = 1? Z = 0? N = 0? PC PC offset B1 M(S) PCH SS-1 M(S) PCL SS-1 M(S) PS SS-1 PCL ADL PCH ADH BRK 3-56 V When T = 1 M(X) M(X) V AND (Note 1) When T = 0 AA M M 29 2 2 25 3 2 0A 2 1 06 5 2 13 4 + 2i 03 4 + 2i 2 17 5 + 2i 07 5 + 2i 3 2 3 "AND's" the contents of accumulator and memory. The results are not entered anywhere. Branches when the contents of negative flag is "1". Branches when the contents of zero flag is "0". Branches when the contents of negative flag is "0". Jumps to address specified by adding offset to the program counter. Executes a software interrupt. 00 7 1 3800 GROUP USER'S MANUAL APPENDIX 3.9 Machine instructions Addressing mode ZP, X OP n 75 4 ZP, Y # OP n 2 ABS # OP n 6D 4 ABS, X # OP n 3 7D 5 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z Z 0 C C # OP n 3 79 5 # OP n 3 # OP n 61 6 # OP n 2 71 6 # OP n 2 NV NV 35 4 2 2D 4 3 3D 5 3 39 5 3 21 6 2 31 6 2 N * * * * * Z * 16 6 2 0E 6 3 1E 7 3 N * * * * * Z C * * * * * * * * * 90 2 2 * * * * * * * * * * * * * * * B0 2 2 * * * * * * * * F0 2 2C 4 3 2 * * * * * * * * M7 M6 * * * * Z * 30 2 2 * * * * * * * * D0 2 2 * * * * * * * * 10 2 2 * * * * * * * * 80 4 2 * * * * * * * * * * * 1 * 1 * * 3800 GROUP USER'S MANUAL 3-57 APPENDIX 3.9 Machine instructions Addressing mode Symbol Function Details IMP OP n BVC (Note 4) BVS (Note 4) CLB V = 0? Branches when the contents of overflow flag is "0". Branches when the contents of overflow flag is "1". Clears the contents of the bit specified in the accumulator or memory to "0". Clears the contents of the carry flag to "0". 18 2 1 1B 2 + 2i 1 1F 5 + 2i 2 IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n # V = 1? Ab or Mb 0 C0 D0 I0 T0 V0 When T = 0 A-M When T = 1 M(X) - M MM X-M CLC CLD Clears the contents of decimal mode flag to D8 2 "0". Clears the contents of interrupt disable flag to "0". Clears the contents of index X mode flag to "0". Clears the contents of overflow flag to "0". 58 2 1 CLI 1 CLT 12 2 1 CLV B8 2 1 CMP (Note 3) Compares the contents of accumulator and memory. Compares the contents of the memory specified by the addressing mode with the contents of the address indicated by index register X. Forms a one's complement of the contents of memory, and stores it into memory. Compares the contents of index register X and memory. Compares the contents of index register Y and memory. Decrements the contents of the accumulator or memory by 1. Decrements the contents of index register X CA 2 by 1. Decrements the contents of index register Y by 1. Divides the 16-bit data that is the contents of M (zz + x + 1) for high byte and the contents of M (zz + x) for low byte by the accumulator. Stores the quotient in the accumulator and the 1's complement of the remainder on the stack. "Exclusive-ORs" the contents of accumulator and memory. The results are stored in the accumulator. "Exclusive-ORs" the contents of the memory specified by the addressing mode and the contents of the memory at the address indicated by index register X. The results are stored into the memory at the address indicated by index register X. Increments the contents of accumulator or memory by 1. Increments the contents of index register X by 1. Increments the contents of index register Y by 1. E8 2 1 88 2 1 C9 2 2 C5 3 2 COM 44 5 2 CPX E0 2 2 E4 3 2 CPY Y-M A A - 1 or MM-1 XX-1 YY-1 A (M(zz + X + 1), M(zz + X)) / A M(S) 1's complememt of Remainder SS-1 When T = 0 - AAVM When T = 1 - M(X) M(X) V M C0 2 2 C4 3 2 DEC 1A 2 1 C6 5 2 DEX DEY 1 DIV EOR (Note 1) 49 2 2 45 3 2 INC A A + 1 or MM+1 XX+1 YY+1 3A 2 1 E6 5 2 INX INY C8 2 1 3-58 3800 GROUP USER'S MANUAL APPENDIX 3.9 Machine instructions Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n 2 # 7 Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C * # OP n # OP n # OP n # OP n # OP n 50 2 NV * * 70 2 2 * * * * * * * * * * * * * * * * * * * * * * * 0 * * * * 0 * * * * * * * * 0 * * * * 0 * * * * * * D5 4 CD 4 0 * * * * * * 2 3 DD 5 3 D9 5 3 C1 6 2 D1 6 2 N * * * * * Z C N EC 4 * * * * * Z * 3 N * * * * * Z C CC 4 3 N * * * * * Z C D6 6 2 CE 6 3 DE 7 3 N * * * * * Z * N * * * * * Z * N E2 16 2 * * * * * Z * * * * * * * * * 55 4 2 4D 4 3 5D 5 3 59 5 3 41 6 2 51 6 2 N * * * * * Z * F6 6 2 EE 6 3 FE 7 3 N * * * * * Z * N * * * * * Z * N * * * * * Z * 3800 GROUP USER'S MANUAL 3-59 APPENDIX 3.9 Machine instructions Addressing mode Symbol Function Details IMP OP n JMP If addressing mode is ABS PCL ADL PCH ADH If addressing mode is IND PCL M (ADH, ADL) PCH M (ADH, ADL + 1) If addressing mode is ZP, IND PCL M(00, ADL) PCH M(00, ADL + 1) M(S) PCH SS-1 M(S) PCL SS-1 After executing the above, if addressing mode is ABS, PCL ADL PCH ADH if addressing mode is SP, PCL ADL PCH FF If addressing mode is ZP, IND, PCL M(00, ADL) PCH M(00, ADL + 1) When T = 0 AM When T = 1 M(X) M M nn XM YM 7 0 0 C Jumps to the specified address. IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n # JSR After storing contents of program counter in stack, and jumps to the specified address. LDA (Note 2) Load accumulator with contents of memory. Load memory indicated by index register X with contents of memory specified by the addressing mode. Load memory with immediate value. A9 2 2 A5 3 2 LDM 3C 4 3 LDX Load index register X with contents of memory. Load index register Y with contents of memory. Shift the contents of accumulator or memory to the right by one bit. The low order bit of accumulator or memory is stored in carry, 7th bit is cleared. Multiplies the accumulator with the contents of memory specified by the zero page X addressing mode and stores the high byte of the result on the stack and the low byte in the accumulator. No operation. EA 2 1 A2 2 2 A6 3 2 LDY A0 2 2 4A 2 1 A4 3 2 LSR 46 5 2 MUL M(S) * A A ! M(zz + X) SS-1 NOP PC PC + 1 When T = 0 AAVM When T = 1 M(X) M(X) V M ORA (Note 1) "Logical OR's" the contents of memory and accumulator. The result is stored in the accumulator. "Logical OR's" the contents of memory indicated by index register X and contents of memory specified by the addressing mode. The result is stored in the memory specified by index register X. 09 2 2 05 3 2 3-60 3800 GROUP USER'S MANUAL APPENDIX 3.9 Machine instructions Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n 4C 3 ABS, X # OP n 3 ABS, Y IND ZP, IND # OP n 3 B2 4 IND, X IND, Y REL SP # OP n # 7 Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C * # OP n # OP n 6C 5 # OP n 2 # OP n # OP n NV * * 20 6 3 02 7 2 22 5 2 * * * * * * * * B5 4 2 AD 4 3 BD 5 3 B9 5 3 A1 6 2 B1 6 2 N * * * * * Z * * * * * * * * * B6 4 B4 4 56 6 2 AE 4 AC 4 4E 6 3 BE 5 3 N * * * * * Z * 2 3 BC 5 3 N * * * * * Z * 2 3 5E 7 3 0 * * * * * Z C 62 15 2 * * * * * * * * * * * * * * * * 15 4 2 0D 4 3 1D 5 3 19 5 3 01 6 2 11 6 2 N * * * * * Z * 3800 GROUP USER'S MANUAL 3-61 APPENDIX 3.9 Machine instructions Addressing mode Symbol Function Details IMP OP n PHA M(S) A SS-1 Saves the contents of the accumulator in memory at the address indicated by the stack pointer and decrements the contents of stack pointer by 1. Saves the contents of the processor status register in memory at the address indicated by the stack pointer and decrements the contents of the stack pointer by 1. Increments the contents of the stack pointer by 1 and restores the accumulator from the memory at the address indicated by the stack pointer. Increments the contents of stack pointer by 1 and restores the processor status register from the memory at the address indicated by the stack pointer. Shifts the contents of the memory or accumulator to the left by one bit. The high order bit is shifted into the carry flag and the carry flag is shifted into the low order bit. Shifts the contents of the memory or accumulator to the right by one bit. The low order bit is shifted into the carry flag and the carry flag is shifted into the high order bit. Rotates the contents of memory to the right by 4 bits. 40 6 1 48 3 IMM # OP n 1 A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n # PHP M(S) PS SS-1 08 3 1 PLA SS+1 A M(S) 68 4 1 PLP SS+1 PS M(S) 28 4 1 ROL 7 0 C 2A 2 1 26 5 2 ROR 7 C 0 6A 2 1 66 5 2 RRF 7 SS+1 PS M(S) SS+1 PCL M(S) SS+1 PCH M(S) SS+1 PCL M(S) SS+1 PCH M(S) 0 82 8 2 RTI Returns from an interrupt routine to the main routine. RTS Returns from a subroutine to the main routine. 60 6 1 SBC (Note 1) (Note 5) When T = 0 AA-M-C When T = 1 M(X) M(X) - M - C Subtracts the contents of memory and complement of carry flag from the contents of accumulator. The results are stored into the accumulator. Subtracts contents of complement of carry flag and contents of the memory indicated by the addressing mode from the memory at the address indicated by index register X. The results are stored into the memory of the address indicated by index register X. Sets the specified bit in the accumulator or memory to "1". Sets the contents of the carry flag to "1". 38 2 1 E9 2 2 E5 3 2 SEB Ab or Mb 1 C1 D1 I1 T1 0B 2 + 2i 1 0F 5 + 2i 2 SEC SED Sets the contents of the decimal mode flag to "1". Sets the contents of the interrupt disable flag to "1". Sets the contents of the index X mode flag to "1". F8 2 1 SEI 78 2 1 SET 32 2 1 3-62 3800 GROUP USER'S MANUAL APPENDIX 3.9 Machine instructions Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C * # OP n # OP n # OP n # OP n # OP n NV * * * * * * * * * * N * * * * * Z * (Value saved in stack) 36 6 2 2E 6 3 3E 7 3 N * * * * * Z C 76 6 2 6E 6 3 7E 7 3 N * * * * * Z C * * * * * * * * (Value saved in stack) * * * * * * * * F5 4 2 ED 4 3 FD 5 3 F9 5 3 E1 6 2 F1 6 2 NV * * * * Z C * * * * * * * * * * * * * * * 1 * * * * 1 * * * * * * * * 1 * * * * 1 * * * * * 3800 GROUP USER'S MANUAL 3-63 APPENDIX 3.9 Machine instructions Addressing mode Symbol Function Details IMP OP n STA MA Stores the contents of accumulator in memory. IMM # OP n A # OP n BIT, A # OP n ZP # OP n 85 4 42 2 BIT, ZP # OP n 2 # STP MX MY XA YA M = 0? XS AX SX AY Stops the oscillator. 1 STX Stores the contents of index register X in memory. Stores the contents of index register Y in memory. Transfers the contents of the accumulator to AA 2 index register X. Transfers the contents of the accumulator to A8 2 index register Y. Tests whether the contents of memory are "0" or not. Transfers the contents of the stack pointer to BA 2 index register X. Transfers the contents of index register X to 8A 2 the accumulator. Transfers the contents of index register X to 9A 2 the stack pointer. Transfers the contents of index register Y to the accumulator. Stops the internal clock. 98 2 1 1 86 4 84 4 2 STY 2 TAX TAY 1 TST 64 3 2 TSX TXA 1 TXS 1 TYA 1 WIT Notes 1 2 3 4 5 C2 2 1 : The number of cycles "n" is increased by 3 when T is 1. : The number of cycles "n" is increased by 2 when T is 1. : The number of cycles "n" is increased by 1 when T is 1. : The number of cycles "n" is increased by 2 when branching has occurred. : N, V, and Z flags are invalid in decimal operation mode. 3-64 3800 GROUP USER'S MANUAL APPENDIX 3.9 Machine instructions Addressing mode ZP, X OP n 95 5 ZP, Y # OP n 2 ABS # OP n 8D 5 ABS, X # OP n 3 9D 6 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C * # OP n 3 99 6 # OP n 3 # OP n 81 7 # OP n 2 91 7 # OP n 2 NV * * * * * * * * * * 96 5 2 8E 5 3 * * * * * * * * 94 5 2 8C 5 3 * * * * * * * * N * * * * * Z * N * * * * * Z * N * * * * * Z * N * * * * * Z * N * * * * * Z * * * * * * * * * N * * * * * Z * * * * * * * * * Symbol IMP IMM A BIT, A ZP BIT, ZP ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP C Z I D B T V N Contents Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit relative addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X-modified arithmetic mode flag Overflow flag Negative flag + - V - V - X Y S PC PS PCH PCL ADH ADL FF nn M V Symbol Contents Addition Subtraction Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address FF in Hexadecimal notation Immediate value Memory specified by address designation of any addressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by ADH and ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits. Contents of address indicated by zero page ADL 1 bit of accumulator 1 bit of memory Opcode Number of cycles Number of bytes M(X) M(S) M(ADH, ADL) M(00, ADL) Ab Mb OP n # 3800 GROUP USER'S MANUAL 3-65 APPENDIX 3.10 List of instruction codes 3.10 List of instruction codes D3 - D0 Hexadecimal notation 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D7 - D4 0 1 2 3 BBS 0, A BBC 0, A BBS 1, A BBC 1, A BBS 2, A BBC 2, A BBS 3, A BBC 3, A BBS 4, A BBC 4, A BBS 5, A BBC 5, A BBS 6, A BBC 6, A BBS 7, A BBC 7, A 4 5 ORA ZP ORA ZP, X AND ZP AND ZP, X EOR ZP EOR ZP, X ADC ZP ADC ZP, X STA ZP STA ZP, X LDA ZP LDA ZP, X CMP ZP CMP ZP, X SBC ZP SBC ZP, X 6 ASL ZP ASL ZP, X ROL ZP ROL ZP, X LSR ZP LSR ZP, X ROR ZP ROR ZP, X STX ZP STX ZP, Y LDX ZP LDX ZP, Y DEC ZP DEC ZP, X INC ZP INC ZP, X 7 BBS 0, ZP BBC 0, ZP BBS 1, ZP BBC 1, ZP BBS 2, ZP BBC 2, ZP BBS 3, ZP BBC 3, ZP BBS 4, ZP BBC 4, ZP BBS 5, ZP BBC 5, ZP BBS 6, ZP BBC 6, ZP BBS 7, ZP BBC 7, ZP 8 9 ORA IMM ORA ABS, Y AND IMM AND ABS, Y EOR IMM EOR ABS, Y ADC IMM ADC ABS, Y -- STA ABS, Y LDA IMM LDA ABS, Y CMP IMM CMP ABS, Y SBC IMM SBC ABS, Y A ASL A DEC A ROL A INC A LSR A -- ROR A -- B SEB 0, A CLB 0, A SEB 1, A CLB 1, A SEB 2, A CLB 2, A SEB 3, A CLB 3, A SEB 4, A CLB 4, A SEB 5, A CLB 5, A SEB 6, A CLB 6, A SEB 7, A CLB 7, A C D ORA ABS E ASL ABS F SEB 0, ZP 0000 BRK JSR ORA IND, X ZP, IND ORA IND, Y AND IND, X AND IND, Y EOR IND, X EOR IND, Y CLT JSR SP SET -- PHP -- 0001 1 BPL JSR ABS BMI -- BIT ZP -- COM ZP -- TST ZP -- STY ZP STY ZP, X LDY ZP LDY ZP, X CPY ZP -- CPX ZP -- CLC -- BIT ABS LDM ZP JMP ABS -- JMP IND -- STY ABS -- LDY ABS CLB ASL ORA ABS, X ABS, X 0, ZP AND ABS ROL ABS SEB 1, ZP 0010 2 PLP 0011 3 SEC CLB ROL AND ABS, X ABS, X 1, ZP EOR ABS LSR ABS SEB 2, ZP 0100 4 RTI STP PHA 0101 5 BVC -- CLI CLB LSR EOR ABS, X ABS, X 2, ZP ADC ABS ROR ABS SEB 3, ZP 0110 6 RTS ADC MUL IND, X ZP, X ADC IND, Y STA IND, X STA IND, Y LDA IND, X -- RRF ZP -- LDX IMM PLA 0111 7 BVS SEI CLB ROR ADC ABS, X ABS, X 3, ZP STA ABS STA ABS, X LDA ABS STX ABS -- LDX ABS SEB 4, ZP CLB 4, ZP SEB 5, ZP 1000 8 BRA DEY TXA 1001 9 BCC LDY IMM BCS CPY IMM BNE CPX IMM BEQ TYA TXS 1010 A TAY TAX 1011 B LDA JMP IND, Y ZP, IND CMP IND, X CMP IND, Y WIT CLV TSX CLB LDX LDA LDY ABS, X ABS, X ABS, Y 5, ZP CPY ABS -- CPX ABS -- CMP ABS DEC ABS SEB 6, ZP 1100 C INY DEX 1101 D -- CLD -- CLB DEC CMP ABS, X ABS, X 6, ZP SBC ABS INC ABS SEB 7, ZP 1110 E SBC DIV IND, X ZP, X SBC IND, Y -- INX NOP 1111 F SED -- CLB INC SBC ABS, X ABS, X 7, ZP 3-byte instruction 2-byte instruction 1-byte instruction 3-66 3800 GROUP USER'S MANUAL APPENDIX 3.11 SFR memory map 3.11 SFR memory map 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port P0 P0 P1 P1 P2 P2 P3 P3 P4 P4 P5 P5 P6 P6 P7 P7 (P0) direction (P1) direction (P2) direction (P3) direction (P4) direction (P5) direction (P6) direction (P7) direction register (P0D) register (P1D) register (P2D) register (P3D) register (P4D) register (P5D) register (P6D) register (P7D) Transmit/Receive buffer register (TB/RB) Serial I/O status register (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 3800 GROUP USER'S MANUAL 3-67 APPENDIX 3.12 Pin configuration 3.12 Pin configuration PIN CONFIGURATION (TOP VIEW) P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15 P37/RD P36/WR P35/SYNC P34/ P33/RESETOUT P32/ONW P31 P30 VCC P71 P70 P67 P66 P65 P64 P63 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 M38002M4-XXXFP M38003M6-XXXHP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 VSS XOUT XIN P40 P41 RESET CNVSS P42/INT0 Package type : 64P6N-A/64P6D-A 64-pin plastic-molded QFP 3-68 P62 P61 P60 P57 P56 P55/CNTR1 P54/CNTR0 P53/INT5 P52/INT4 P51/INT3 P50/INT2 P47/SRDY P46/SCLK P45/TXD P44/RXD P43/INT1 3800 GROUP USER'S MANUAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 APPENDIX 3.12 Pin configuration PIN CONFIGURATION (TOP VIEW) VCC P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55/CNTR1 P54/CNTR0 P53/INT5 P52/INT4 P51/INT3 P50/INT2 P47/SRDY P46/SCLK P45/TXD P44/RXD P43/INT1 P42/INT0 CNVSS RESET P41 P40 XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30 P31 P32/ONW P33/RESETOUT P34/ P35/SYNC P36/WR P37/RD P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15 P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 Package type : 64P4B 64-pin shrink plastic-molded DIP 3800 GROUP USER'S MANUAL M38002M4-XXXSP 3-69 MITSUBISHI SEMICONDUCTORS USER'S MANUAL 3800Group Mar. First Edition 1996 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. (c)1996 MITSUBISHI ELECTRIC CORPORATION User's Manual 3800 Group MITSUBISHI ELECTRIC CORPORATION HEAD OFFICE: MITSUBISHI DENKI BLDG., MARUNOUCHI, TOKYO 100. TELEX: J24532 CABLE: MELCO TOKYO H-EE418-A KI-9603 Printed in Japan (ROD) (c) 1996 MITSUBISHI ELECTRIC CORPORATION New publication, effective Mar. 1996. Specifications subject to change without notice. |
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